Shift Register Sub-Circuit Design for Signal Fall Time Reduction
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Solution Overview
Problem
Existing shift registers in display technology face challenges in achieving high driving ability, particularly in reducing fall time of signal output, which affects the performance and reliability of display devices using OLEDs or QLEDs.
Innovation Solution
The proposed shift register incorporates a specific configuration of control sub-circuits, including a first control sub-circuit, a second control sub-circuit, a pull-up control sub-circuit, and an output control sub-circuit, which are electrically connected to provide efficient signal control and output. This configuration allows for quick provision of a high-level signal to the first node, thereby reducing signal fall time and enhancing driving ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional shift register configuration is used, then device complexity is reduced, but signal fall time increases and driving ability decreases
Solution Approach 1:
The shift register is divided into multiple functional sub-circuits: first control sub-circuit (T1-T4, C1), second control sub-circuit (T5-T6), pull-up control sub-circuit (T3), and output control sub-circuit (T7-T10, C2, C3). Each sub-circuit performs a specific function in the signal transmission process, allowing optimized control of signal rise and fall times while maintaining modular design benefits
Solution Approach 2:
The pull-up control sub-circuit proactively provides a high-level signal to the first node in advance to prepare for quick signal transitions. The first control sub-circuit pre-charges nodes and prepares transistor states before the main signal transition occurs, reducing the overall fall time of the output signal
2Power
If conventional control configuration is used, then ease of manufacture is improved, but driving ability and signal control precision deteriorate
Solution Approach 1:
Different sub-circuits are assigned specific local functions with optimized transistor configurations. The first control sub-circuit uses T1-T4 with specific gate connections for signal input control, while the output control sub-circuit uses T7-T10 for optimized output driving. Each transistor's gate, source, and drain are strategically connected to provide localized signal control optimization
Solution Approach 2:
The first node serves multiple functions: it receives signals from the first control sub-circuit, accepts pull-up control from the pull-up control sub-circuit, and provides control signals to the output control sub-circuit. This multi-functional design reduces the need for additional dedicated components while maintaining high driving ability
Data Source
AI summary
A shift register includes a first control sub-circuit, a second control sub-circuit, a pull-up control sub-circuit and an output control sub-circuit, wherein the first control sub-circuit is configured to provide a signal of a third power supply terminal or a clock signal terminal to a first node and a third node under the control of a signal input terminal, the clock signal terminal and a second node; the pull-up control sub-circuit is configured to provide a signal of a second power supply terminal to the first node under the control of the third node; the second control sub-circuit is configured to provide a signal of the signal input terminal to the second node and a fourth node under the control of the clock signal terminal and the first power supply terminal.