Shift Register Element Feedback Control for Display Stability
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Solution Overview
Problem
The stability of display screen gate driving circuits, particularly shift register elements, is compromised due to susceptibility to external interference, leading to output errors.
Innovation Solution
A shift register element design incorporating an output module, first and second drivers, and feedback and adjustment modules to control node voltages based on input and output signals, preventing floating states and external interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If nodes are left floating to maintain potential by capacitors, then the circuit structure is simpler, but the circuit becomes susceptible to external interference and produces output errors
Solution Approach 1:
The patent implements feedback control by using the output signal to control the state of nodes N1 and N2 through transistors M4 and M5. The output module detects the output state and feeds it back to adjust the node potentials, ensuring they remain stable and resistant to external interference while maintaining circuit reliability.
2Use of energy by moving object
If nodes are kept floating during non-active periods, then energy consumption is reduced, but the nodes become vulnerable to external signals and interference
Solution Approach 1:
The patent applies preliminary action by proactively setting the potentials of nodes N1 and N2 to specific levels (high or low) based on the output state before external interference can affect them. The feedback control mechanism pre-establishes stable potential states during non-active periods, preventing vulnerability to external signals while maintaining energy efficiency.
Data Source
AI summary
A shift register element, a method for driving the same, and a display device are disclosed. The shift register element includes: an output module configured to provide an output terminal with a signal of a first signal terminal or a second signal terminal by voltage applied to a first node and a second node; a first driver configured to control voltage of the first node by the signal of the first input terminal; a second driver configured to control voltage of the second node by the signal of the first input terminal, and a signal of a third input terminal; a first feedback and adjustment module configured to control the voltage of the first node by the signals of the output terminal and the second input terminal; and a second feedback and adjustment module configured to control the voltage of the second node by the signal of the output terminal.


