Shift Register Circuit for Display Panel Flicker Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In active matrix display devices, shift registers induce visible flicker due to imbalance in voltage falling speed between the far end and near end of gate lines, which is exacerbated in high-resolution displays.
Innovation Solution
A shift register design comprising cascaded units with specific switch and capacitor configurations, utilizing clock signals to control the transition speed of output signals, ensuring fast rising edges and slow falling edges to minimize voltage imbalance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transition speed on the falling edge of the output signal is fast, then the response speed of the shift register is improved, but visible flicker is induced due to voltage imbalance between far end and near end of the gate line
Solution Approach 1:
The patent applies local quality by differentiating the transition speed control for rising edges and falling edges. The circuit configuration allows fast rising edges for quick signal activation while implementing slow falling edges through specific capacitor and switch arrangements to prevent voltage imbalance and flicker. Each shift register unit has customized timing characteristics for different signal transitions.
Solution Approach 2:
The patent changes the transition speed parameter dynamically by using different time constants for rising and falling edges. Through the configuration of capacitors (C1, C2) and switches (S1-S6), the circuit achieves fast rising edges with one time constant and slow falling edges with another time constant, optimizing both response speed and flicker prevention.
2Object-affected harmful factors
If the transition speed on the falling edge is slowed down to reduce flicker, then voltage imbalance is minimized, but the response speed of the shift register deteriorates
Solution Approach 1:
The patent segments the signal transition into two independent phases: rising edge and falling edge. By controlling these phases separately through different circuit configurations (different capacitors and switch combinations), the patent can optimize each phase independently - fast rising edge for response speed and slow falling edge for voltage balance.
Solution Approach 2:
The patent implements dynamic control of transition speeds by using clock signals (CLK1, CLK2) that can be adjusted in timing. The circuit dynamically switches between different time constants based on the operational phase, allowing the system to adapt its response characteristics to minimize both flicker and maintain speed performance.
Data Source
AI summary
A shift register is provided. In each of successively cascaded shift register units, for a first switch, control and output terminals are coupled to a first node and an output node respectively, and an input terminal receives a first clock signal. For a second switch, input and output terminals are coupled to the control terminal of the second switch and the first node respectively. For a third switch, a control terminal is coupled to the first node, and an input terminal receives the first clock signal. A first capacitor is coupled between an output terminal of the third switch and the first node. For a fourth switch, an input terminal is coupled to the first node, and an output terminal is coupled to a low voltage terminal. For a current shift register, a control terminal of the second switch receives an output signal generated by previous shift register unit.