Shift Register Flip-Flop Merging for IC Power and Area Reduction
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Solution Overview
Problem
Conventional multibit techniques do not effectively apply to flip-flops in shift registers, leading to increased resource consumption and power usage in integrated circuit designs, particularly in designs with large numbers of functional shift registers.
Innovation Solution
Applying a physically aware multibit cell merging approach to merge functional shift register flip-flops into non-scan multibit flops during synthesis, allowing for serial or parallel configurations based on physical proximity, thereby reducing area, scan-wirelength, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional multibit techniques are applied to flip-flops in shift registers, then resource consumption and power usage are reduced, but the techniques are not effectively applicable to shift register flip-flops
Solution Approach 1:
The patent merges functional shift register flip-flops into non-scan multi-bit flip-flops during synthesis, combining multiple individual flip-flops into a single multi-bit cell. This merging reduces the total number of flip-flop instances and their associated resources, thereby reducing power consumption while maintaining the shift register functionality through serial or parallel configurations based on physical proximity
2Area of stationary object
If multibit cell merging is applied to shift registers, then area and scan-wirelength are reduced, but synthesis complexity increases
Solution Approach 1:
The patent performs shift register identification and multibit cell merging during the synthesis phase, before physical layout and routing. By preliminarily identifying shift registers and merging their flip-flops into multi-bit cells during synthesis, the design automatically optimizes area and scan-wirelength without requiring manual intervention or complex post-processing steps, thus managing synthesis complexity through automated early-stage optimization
3Device complexity
If functional shift register flip-flops are merged into non-scan multi-bit flops, then wiring congestion is reduced, but scan chain functionality must be maintained
Solution Approach 1:
The patent applies different merging strategies to different parts of the shift register based on their physical proximity and functional requirements. Flip-flops that are physically close together are merged into multi-bit cells to reduce wiring congestion locally, while maintaining scan chain functionality through proper configuration of the multi-bit cells. This localized approach allows optimization of wiring congestion without compromising overall scan chain reliability
Data Source
AI summary
Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.