Shift Register Four Phase Clocks Reduce Transistor Stress
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Solution Overview
Problem
Conventional shift registers in LCD driving circuits, using amorphous silicon or low temperature polycrystalline silicon thin film transistors, face reliability issues due to prolonged activation of transistors under high-frequency clock signals, leading to deterioration and reduced performance.
Innovation Solution
A shift register design incorporating four phase clocks with distinct frequencies and phases, where each stage receives a specific combination of clock signals based on odd or even numbering, and includes a series of transistors and discharge control circuits to manage signal shifting and voltage supply, reducing transistor stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-frequency clock signals are used to shift output signals quickly, then productivity is improved, but transistor stress increases leading to reliability deterioration
Solution Approach 1:
The clock signal system is segmented into four distinct phases (CLK1, CLK2, XCLK1, XCLK2) with different frequencies and phases. Odd stages receive one clock combination while even stages receive another, dividing the uniform clocking approach into differentiated segments that reduce simultaneous transistor activation and stress across the shift register stages.
2Speed
If multiple clock signals with same high frequency are applied to shift signals rapidly, then speed is improved, but transistor stress and deterioration increase
Solution Approach 1:
Different clock signal combinations are applied to different stages of the shift register. Odd stages receive clock signals with a specific frequency and phase relationship, while even stages receive clock signals with different frequency and phase characteristics. This local differentiation ensures that transistors in different stages experience different stress patterns, preventing uniform deterioration while maintaining high-speed operation.
Solution Approach 2:
The patent employs periodic clock signals with specific phase relationships (including inverted phases) to control transistor switching. By using periodic action with varied frequencies and phases across different stages, the system achieves rapid signal transmission while distributing stress periodically rather than continuously, reducing cumulative transistor deterioration.
Data Source
AI summary
A shift register comprising means for providing a first pair of clock signals, CLK1 and XCLK1, with a first frequency, f1, and a second pair of clock signals, CLK2 and XCLK2, with a second frequency, f2, where the second frequency f2 is different from the first frequency f1, and means for generating a plurality of signals responsive to a start pulse signal, the first pair of clock signals CLK1 and XCLK1, and the second pair of clock signals CLK2 and XCLK2. Each of the plurality of signals is sequentially shifted from the start pulse signal.