Shift Register Gate Boosting for High-Frequency Display Driving
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Solution Overview
Problem
Conventional shift register circuits face a reduction in driving capability when operating at high clock signal frequencies due to the third transistor operating in a source follower mode, which limits the pre-charging of the first node and reduces the gate-source voltage of the first transistor, hindering the rapid charging and activation of gate lines in display apparatus.
Innovation Solution
The introduction of a charging circuit and a boosting circuit that charge and boost a second node, allowing the first node to be pre-charged with the third transistor performing a non-saturated operation, thereby maintaining a high gate-source voltage and enhancing the driving capability of the first transistor, even at high clock signal frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is increased to improve the operation speed of the shift register circuit, then the productivity is improved, but the driving capability of the first transistor is reduced due to insufficient pre-charging of the first node
Solution Approach 1:
The invention introduces a preliminary pre-charging action by adding a fourth transistor connected between the second power-supply terminal and the first node. This fourth transistor activates before the clock signal transitions, pre-charging the first node to a high level. This preliminary action ensures that when the clock signal rises, the first transistor already has sufficient gate-source voltage to immediately enter saturation mode and drive the output terminal to the high level rapidly, thus maintaining high driving capability even at increased clock frequencies.
2Device complexity
If the third transistor operates in source follower mode to simplify the circuit structure, then the device complexity is reduced, but the pre-charging capability of the first node is limited, reducing the gate-source voltage of the first transistor
Solution Approach 1:
The invention segments the pre-charging function by introducing a dedicated fourth transistor specifically for pre-charging the first node, separating this function from the third transistor which operates in source follower mode. This segmentation allows the fourth transistor to provide full-strength pre-charging current directly to the first node without the voltage loss characteristic of source follower operation, thereby achieving high gate-source voltage for the first transistor while maintaining relatively simple circuit structure.
Data Source
AI summary
In a shift register circuit, a reduction of a driving capability caused by an increased operating rate is prevented. A shift register circuit includes a first transistor between an output terminal and a clock terminal, a second transistor between the output terminal and a first power-supply terminal, and a third transistor between the gate of the first transistor and a second power-supply terminal. The shift register circuit further includes a fourth transistor that charges the gate node of the third transistor on the basis of a signal inputted to a first input terminal, and a capacitive element that boosts the gate node of the third transistor that has been charged.