Shift Register Circuit for Faster Gate-Line Charging in Displays

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Solution Overview

Problem

Conventional shift register circuits used in image display apparatuses, such as liquid crystal displays, face challenges in speeding up the charging of gate electrodes due to large capacitive loads, which slows down the operation of the gate line driving circuit, especially when using field-effect transistors of the same conductivity type.

Innovation Solution

The proposed shift register circuit includes specific configurations with multiple transistors and input/output terminals that allow for faster charging of the gate electrode by inputting signals with faster level transitions, enabling the operation of transistors in a nonsaturated region and improving drive capabilities, thus accelerating level transitions of output signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the channel width of the output pull-up transistor is increased to improve drive capability, then the speed of level transitions is improved, but the circuit area increases

Engineering Contradiction:
Improvespeed of level transitionsVSAvoidcircuit area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The gate electrode of the output pull-up transistor is precharged to a high potential before signal output through a charger transistor. This preliminary charging action ensures that the gate-source voltage remains high during signal output, maintaining high drive capability without requiring an increased channel width, thus avoiding the area penalty

Inventive Principle:
Principle #10Preliminary action

2Power

If the gate potential of the output pull-up transistor is increased to maintain high gate-source voltage during signal output, then the drive capability is improved, but the charging time required increases

Engineering Contradiction:
Improvedrive capabilityVSAvoidcharging time
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The charger transistor is diode-connected (gate connected to drain), creating a copy of the output signal at the gate of the output pull-up transistor. This diode-connected configuration allows the gate electrode to be charged to the same potential level as the output signal, ensuring high gate-source voltage during output without requiring excessive charging time

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If conventional shift register circuits are used with large capacitive loads (gate lines), then the gate line driving function is achieved, but the rising speeds of output signals become slow

Engineering Contradiction:
Improvegate line driving functionVSAvoidrising speeds of output signals
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The charger transistor acts as an intermediary between the output signal and the gate electrode of the output pull-up transistor. It transfers the output signal voltage to the gate electrode through capacitive coupling, ensuring that the gate-source voltage remains high even when driving large capacitive loads like gate lines, thus maintaining fast rising speeds despite the heavy load

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7738623B2Shift register circuit and image display apparatus containing the same
Publication Date: 2010.06.15 TRIVALE TECHNOLOGIES LLC
  • US7738623B2 patent drawing
  • US7738623B2 patent drawing
  • US7738623B2 patent drawing

AI summary

A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.