Shift Register Gate Control to Prevent Coupling-Induced Misoperation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing shift register circuits used in gate line drive circuits for liquid crystal displays face issues with defective operation during non-selected periods and reduced drive capability during signal output, due to the interaction between capacity elements and clock signals, which hinders high-speed operation and image display quality.
Innovation Solution
A shift register circuit design that includes a switching circuit to control the control electrode of the first transistor, ensuring it remains discharged during non-selected periods and effectively charged during signal output, thereby preventing unnecessary activation and maintaining high drive capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a first transistor is provided as an output pull-up transistor connected between a first clock terminal and an output terminal, then the number of transistors is decreased, but the gate potential rises due to coupling through overlap capacity causing defective operation
Solution Approach 1:
A second transistor is introduced as an intermediary component between the first transistor and the first clock terminal. This second transistor acts as a mediator to control the coupling effect, preventing the gate potential from rising due to overlap capacity while maintaining the simplified transistor structure. The second transistor selectively connects or disconnects the first clock terminal from the first transistor based on the state of a third transistor, thereby eliminating the defective operation caused by direct coupling.
2Loss of energy
If the first transistor is kept in off state during non-output period, then power consumption is reduced, but the gate potential tries to rise due to coupling causing unnecessary activation
Solution Approach 1:
The second transistor is configured to preemptively prevent the coupling effect before it can cause unnecessary activation. When the third transistor is in a specific state, the second transistor disconnects the first clock terminal from the first transistor, thereby preventing the gate potential from rising due to overlap capacity coupling. This preliminary anti-action ensures that the first transistor remains reliably in the off state during non-output periods, preventing unnecessary activation while maintaining low power consumption.
3Reliability
If a capacity element is used to prevent gate potential variation, then defective operation is prevented, but drive capability is lowered and high-speed operation becomes difficult
Solution Approach 1:
Instead of using a capacity element that would slow down the circuit, a second transistor is introduced as an intermediary to control the coupling effect dynamically. This transistor-based solution prevents gate potential variation and defective operation without introducing significant capacitance that would hinder high-speed operation. The second transistor can rapidly switch states to prevent unwanted coupling, maintaining both reliability and speed performance.
4Reliability
If the gate potential is held constant to prevent defective operation, then reliability is improved, but the voltage between gate and source is lowered reducing drive capability
Solution Approach 1:
The circuit employs dynamic control through the second and third transistors to manage the gate potential. Rather than holding the gate potential constant, the second transistor dynamically prevents coupling-induced potential rises only when necessary (when the third transistor indicates a specific state). This dynamic approach maintains reliability by preventing defective operation while preserving drive capability during normal operation when the gate-source voltage needs to be high.
Data Source
AI summary
In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.