Shift Register Gate Control for Reliable LCD Line Driving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing shift register circuits used in gate line drive circuits for liquid crystal displays face issues with defective operation during non-selected periods and reduced drive capability during signal output, due to the antinomy between capacity elements that prevent potential rise and ensure drive capability.
Innovation Solution
A shift register circuit design that includes a switching circuit to control the transistor's control electrode, ensuring high drive capability by allowing the control electrode to rise sufficiently during signal output and discharge to a low level during non-selected periods, preventing unnecessary activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacity element is added to prevent gate potential rise during non-selected periods, then defective operation is prevented, but drive capability is reduced during signal output
Solution Approach 1:
The patent applies the dynamics principle by making the switching circuit's on/off state change dynamically based on the clock signal phase. During the first clock phase, the switching circuit is on to allow sufficient gate potential rise for high drive capability. During the second clock phase, the switching circuit is off to prevent gate potential rise and maintain low leakage current. This dynamic switching resolves the contradiction between reliability and drive capability.
Solution Approach 2:
The patent applies periodic action by using clock signals with different phases to periodically control the switching circuit. The switching circuit is turned on during the first clock phase and off during the second clock phase, creating a periodic pattern that alternates between high drive capability mode and low leakage current mode, thereby resolving the technical contradiction.
2Power
If the control electrode is allowed to rise sufficiently during signal output, then drive capability is enhanced, but unnecessary activation occurs during non-selected periods
Solution Approach 1:
The patent uses dynamic switching control where the switching circuit's state changes based on clock signal phases. During the first clock phase, the switching circuit is on, allowing the control electrode to rise sufficiently for high drive capability. During the second clock phase, the switching circuit is off, preventing unnecessary activation. This dynamic control resolves the contradiction between drive capability and operation reliability.
Solution Approach 2:
The patent implements feedback control through the clock signal that regulates the switching circuit's operation. The clock signal provides timing feedback that controls when the switching circuit should be on or off, ensuring the control electrode rises sufficiently during signal output phases while preventing unnecessary activation during non-selected periods, thereby resolving the contradiction.
Data Source
AI summary
In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.