Shift Register Circuit for Gate Driver Output Stability

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Solution Overview

Problem

The existing pixel driving circuits in display technologies face challenges in achieving high charge mobility and stability while requiring low production costs, particularly due to the limitations of N-type oxide TFTs for scan and reset transistors and LTPS TFTs for switching and driving transistors, which affect the output ability of gate driver circuits.

Innovation Solution

A shift register design is introduced, incorporating input, control, and output circuits with specific transistor configurations and signal transmission mechanisms to manage voltage signals and clock signals effectively, ensuring high voltage levels for N-type transistors and low voltage levels for P-type transistors, thereby enhancing the output capability of the gate driver circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If N-type oxide TFTs are used for scan and reset transistors, then low leakage rate is achieved, but charge mobility is limited

Engineering Contradiction:
Improveleakage rateVSAvoidcharge mobility
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies different transistor types to different functional blocks: N-type oxide TFTs are used specifically for scan and reset transistors where low leakage is critical, while LTPS TFTs are used for switching and driving transistors where high charge mobility is required. This local differentiation resolves the contradiction by optimizing each component for its specific functional requirement rather than using a uniform transistor type throughout the circuit.

Inventive Principle:
Principle #3Local quality

2Speed

If LTPS TFTs are used for switching and driving transistors, then charge mobility is improved, but production cost increases

Engineering Contradiction:
Improvecharge mobilityVSAvoidproduction cost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent strategically deploys LTPS TFTs only in specific blocks (switching and driving transistors) where high charge mobility provides the most benefit, while using the lower-cost N-type oxide TFTs in other blocks (scan and reset transistors). This selective application reduces overall production costs compared to using LTPS TFTs throughout the entire circuit, while still achieving high charge mobility where it is most needed for the switching and driving functions.

Inventive Principle:
Principle #3Local quality

3Reliability

If mixed transistor types are used in pixel driving circuit, then performance is improved, but circuit complexity increases

Engineering Contradiction:
ImprovestabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the pixel driving circuit into distinct functional blocks (scan transistor block, reset transistor block, switching transistor block, driving transistor block) and assigns specific transistor types to each block. This segmentation allows the circuit to achieve improved performance through mixed transistor types while managing complexity by organizing the mixed technology into clear, functional segments with well-defined roles.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11862216B2Shift register and driving method therefor, gate driver circuit, and display apparatus
Publication Date: 2024.01.02 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US11862216B2 patent drawing
  • US11862216B2 patent drawing
  • US11862216B2 patent drawing

AI summary

A shift register, comprising an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to transmit a first voltage signal from a first voltage signal terminal to a first node under the control of an input signal from a signal input terminal. The first control circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a second node under the control of a first clock signal from a first clock signal terminal and the voltage of the first node. The second control circuit is configured to transmit a second clock signal from a second clock signal terminal to a third node under the control of the voltage of the second node. The output circuit is configured to transmit the first voltage signal from the first voltage signal terminal to a scan signal output terminal under the control of the voltage of the third node.