Shift Register Circuit Layout for Stable OLED/QLED Gate Driving
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Solution Overview
Problem
Existing display technologies face challenges in efficiently driving flexible displays using Thin Film Transistors (TFTs) for OLED and QLED devices, particularly in ensuring stable signal control and efficient power supply to the drive circuits.
Innovation Solution
A shift register circuit comprising multiple control and output sub-circuits, connected through specific transistor and capacitor configurations, to manage signal and power supply control, ensuring stable operation and efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional shift register circuit is used in OLED/QLED display devices, then the basic signal control function is achieved, but the signal stability and power supply efficiency are insufficient
Solution Approach 1:
The shift register circuit is divided into multiple independent control sub-circuits (first control sub-circuit, second control sub-circuit, third control sub-circuit) and output sub-circuits. Each sub-circuit handles specific control functions, allowing modular optimization of signal stability without requiring complete circuit redesign. This segmentation enables targeted improvements in reliable sub-circuits while maintaining overall system manageability.
Solution Approach 2:
The circuit employs dynamic clock signal control with at least two different clock signals (first clock signal and second clock signal) that can be independently adjusted. The control sub-circuits dynamically switch between different operating states based on signal requirements, enabling adaptive optimization of signal stability and power consumption characteristics during different display refresh phases.
2Ease of manufacture
If the drive circuit is simplified to reduce manufacturing complexity, then ease of manufacture is improved, but signal control precision and power management efficiency deteriorate
Solution Approach 1:
The control sub-circuits are designed with multi-functional capabilities, where each sub-circuit can perform multiple control operations (signal level adjustment, clock synchronization, power gating) using the same basic transistor and capacitor structures. This universal design approach maintains signal control precision while reducing the variety of unique circuit elements that need to be manufactured, thereby easing fabrication processes.
Solution Approach 2:
The circuit utilizes parameter adjustment of existing components (transistor threshold voltages, capacitor values, clock signal frequencies) to achieve precise signal control without adding complex circuit topologies. By optimizing electrical parameters of standard TFT and capacitor structures, the design maintains high signal control precision while using manufacturable component specifications.
3Reliability
If more control sub-circuits are added to improve signal control, then signal stability is enhanced, but power consumption increases
Solution Approach 1:
The control sub-circuits operate in periodic cycles synchronized with the display refresh rate, activating only when needed for signal updates. The clock signals are pulsed rather than continuous, allowing control transistors to remain in high-impedance states during idle periods. This periodic operation maintains signal control stability through regular synchronization while minimizing static power consumption between update cycles.
Solution Approach 2:
The circuit extracts and separates the power management function into dedicated power control transistors within each control sub-circuit. These extracted power control elements can independently gate the supply voltage to specific circuit blocks, allowing power to be completely cut off from inactive sub-circuits while maintaining operational sub-circuits at full power, thus reducing total power consumption while preserving signal stability in active regions.
Data Source
AI summary
Disclosed is a shift register, comprising: a first control sub-circuit, which provides a signal of a signal input end for a first node; a second control sub-circuit, which provides a signal of a second power source end or a signal of the first clock signal end for the second node; a third control sub-circuit, which provides a signal of the second clock signal end or a signal of the first power source end for a fourth node and maintains the potential of the fourth node; a first output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a first signal output end; and a second output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a second signal output end.