Shift Register Gate-Shaping Circuit for Display Flicker Reduction
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Solution Overview
Problem
Conventional gate driving circuits in display panels experience issues such as flickers and residual images due to large voltage changes at pixel electrodes caused by coupling capacitance between the gate and drain of display transistors, leading to ineffective scanning signals.
Innovation Solution
A shift register design with specific configurations, including input, reset, node control, gate-shaping control, and output units, that manage clock signals with different voltage amplitudes and phases to maintain a stable voltage difference and opposite potentials between nodes, ensuring accurate and stable scanning signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate driving circuits are used, then the circuit structure is simple, but large voltage changes occur at pixel electrodes causing flickers and residual images
Solution Approach 1:
The gate driving circuit is divided into multiple shift register stages, with each stage independently controlling a segment of gate lines. This segmentation allows for better voltage control and reduces the impact of coupling capacitance on the entire display panel, thereby reducing flickers and residual images while maintaining reasonable circuit complexity
Solution Approach 2:
The circuit performs preliminary resetting of the first node before signal input to eliminate residual voltage effects. By preemptively clearing the node state and controlling the timing of signal transmission, the circuit prevents voltage accumulation that would otherwise cause display artifacts, improving reliability without significantly increasing complexity
2Stability of the object's composition
If the first node is kept floating to maintain voltage difference, then stable voltage difference is achieved, but the node is vulnerable to noise and interference
Solution Approach 1:
The first node is periodically reset to reference potential at specific timing intervals rather than being continuously connected or left floating. This periodic resetting maintains the voltage difference stability while minimizing the node's exposure to noise and interference, as the node is only floating during necessary signal transmission periods
Solution Approach 2:
The reset signal terminal acts as an intermediary that periodically connects the first node to the reference potential. This intermediary connection stabilizes the node voltage without requiring continuous connection, thereby maintaining voltage difference stability while reducing vulnerability to noise during critical signal transmission periods
Data Source
AI summary
The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit, a first reset unit, a node control unit, a gate-shaping unit, a first output unit and a second output unit. The shift register is configured to change a potential of a scan signal outputted from a driving signal output terminal, so as to produce a scan signal having a gate-shaped waveform.