Shift Register Gating for Variable-Width Low-Power Operation

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Solution Overview

Problem

Conventional shift registers consume energy unnecessarily when the number of bits required for data computation is less than the total number of bits, as all flip-flops remain active, leading to inefficiency.

Innovation Solution

A shift register design that disables unused flip-flops based on the input data stored, utilizing a gating circuit to control the clock and power supply to inactive flip-flops, entering a low power mode when unnecessary flip-flops are detected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If all flip-flops remain active in conventional shift registers, then the shift register can handle maximum data width, but power consumption increases unnecessarily when fewer bits are needed

Engineering Contradiction:
Improvepower consumptionVSAvoiddata width handling capability
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The shift register dynamically adjusts the number of active flip-flops based on the actual data width being processed. The gating circuit enables or disables flip-flops in real-time according to the input data requirements, transitioning the system from a static all-active state to a dynamic adaptive state that optimizes power consumption while maintaining versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different flip-flops are assigned different operational states (enabled or disabled) based on their position and the actual data width. Instead of uniform activation, the system applies local quality control where only the necessary portion of flip-flops remain active, while others are gated off to save power.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If unused flip-flops are disabled to reduce power consumption, then energy efficiency improves, but the shift register cannot adapt to varying data widths

Engineering Contradiction:
Improveenergy wasteVSAvoidflexibility in data processing
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The gating circuit receives feedback about the actual data width being processed and uses this information to control the enable/disable state of flip-flops. This feedback mechanism ensures that the shift register adapts its power consumption to match the actual computational needs, eliminating energy waste while preserving adaptability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The gating circuit serves multiple functions: it acts as a power management device to reduce energy consumption, while simultaneously serving as a configuration device that enables the shift register to handle variable data widths. This multi-functionality resolves the contradiction between energy efficiency and adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If a gating circuit is added to control flip-flop activation, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The gating circuit acts as an intermediary component between the input data and the flip-flops. It mediates the control signal flow, enabling or disabling flip-flops based on data width requirements. This intermediary approach achieves power reduction with minimal added complexity, as the gating logic can be integrated efficiently into the existing shift register architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12362027B2Shift register having low power mode
Publication Date: 2025.07.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12362027B2 patent drawing
  • US12362027B2 patent drawing
  • US12362027B2 patent drawing

AI summary

The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.