Shift Register Glitch-Free Operation in Power Saving Mode
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Solution Overview
Problem
Shift registers in semiconductor memory devices, such as DRAM, experience glitches during transitions between power-saving and active modes, leading to erroneous control signals and data shifts, which hinder efficient data access operations.
Innovation Solution
A shift register design incorporating a drive operation controller with a first logic gate, a flip-flop, an inverter, and a second logic gate to generate a glitch-free clock signal, ensuring seamless operation between power-saving and active modes by retiming the clock enable signal and applying it to subsequent flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the shift register operates in power-saving mode with the clock turned off, then power consumption is reduced, but glitch-free operation cannot be maintained when transitioning to active mode
Solution Approach 1:
The drive operation controller prepares the clock enable signal in advance by retiming it with respect to the first clock before it is needed for the second clock generation. This preliminary retiming ensures that when the shift register transitions from power-saving mode to active mode, the clock signal is already properly synchronized and ready to drive the flip-flops without causing glitches, thus maintaining reliability while enabling power-saving operation.
2Speed
If the toggling clock is immediately restored upon data input during power-saving mode, then data access speed is maintained, but glitch generation occurs during mode transition
Solution Approach 1:
The drive operation controller acts as an intermediary between the first clock and the second clock signals. It receives the first clock, retimes the clock enable signal with respect to this first clock, and then generates the second clock that drives the flip-flops. This intermediary retiming process ensures smooth transition between power-saving and active modes, preventing glitches while maintaining fast data access capability.
3Device complexity
If a simple clock distribution is used in the shift register, then device complexity is reduced, but glitch-free operation during mode transitions cannot be ensured
Solution Approach 1:
The clock distribution is segmented into two distinct clock signals: a first clock that drives the drive operation controller and a second clock that drives the flip-flops in the shift register. This segmentation allows independent optimization of each clock path, with the first clock used for control signal retiming and the second clock for data shifting, thereby ensuring glitch-free operation during mode transitions while keeping the overall complexity manageable.
Data Source
AI summary
Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller. The drive operation controller includes; a first logic gate configured to receive and logically combine selected outputs from selected ones of the plurality of flip-flops to generate a gate output signal, a drive operation controller flip-flop configured to receive the gate output signal and retime the gate output signal in response to a first clock applied to a clock terminal of a first flip-flop in the plurality of flip-flops to generate a clock enable signal, an inverter configured to receive the clock enable signal and generate an inverted clock enable signal, and a second logic gate configured to receive and logically combine the first clock and the inverted clock enable signal to generate a second clock, wherein the second clock signal is applied to a clock terminal of at least one later stage flip-flop following the first flip-flop in the plurality of flip-flops.