Shift Register Gate Driver With Pull-Down Glitch Suppression

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Solution Overview

Problem

Existing gate drivers and shift registers suffer from glitches caused by the coupling effect of parasitic capacitors, leading to incorrect waveform generation and potential wrong charging of pixels due to the inability to effectively suppress these glitches instantly.

Innovation Solution

The introduction of a stability pull-down control circuit with specific switches and a driving circuit that manages electrical connections based on voltage levels, providing a discharging path before clock signal changes, effectively suppressing glitches and maintaining stable voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a bidirectional shift register is used to provide gate driving signals, then the gate driver can control multiple pixels, but glitches are generated due to the coupling effect of parasitic capacitors

Engineering Contradiction:

Improvecontrol capabilityVSAvoidglitches

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by introducing a stability pull-down control circuit that activates before the clock signal transitions. This circuit proactively suppresses potential glitches by maintaining the node voltage at a stable level during critical transition periods, preventing the coupling effect of parasitic capacitors from generating harmful voltage fluctuations.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The stability pull-down control circuit acts as an intermediary between the parasitic capacitors and the output node. It mediates the harmful coupling effect by providing a controlled discharge path through switch T1D, which is activated by the stability pull-down control signal to counterbalance the voltage fluctuations caused by parasitic capacitor coupling.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If switches are used to control electrical connections in the shift register, then signal routing is achieved, but voltage level instability occurs due to parasitic capacitor coupling

Engineering Contradiction:

Improvesignal routingVSAvoidvoltage level

Core Design Contradiction:

Ease of operationVSStability of the object's composition

Solution Approach 1:

The stability pull-down control circuit performs preliminary action by preparing the discharge path before the clock signal transitions. Switch T1D is controlled by the stability pull-down control signal to activate in advance, ensuring the node voltage remains stable during the upcoming signal transition, thereby preventing voltage level instability caused by parasitic capacitor coupling.

Inventive Principle:

Principle #10Preliminary action

3Speed

If the clock signal transitions rapidly to update gate driving signals, then signal update speed is improved, but glitches are generated due to parasitic capacitor coupling

Engineering Contradiction:

Improvesignal update speedVSAvoidglitches

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

The stability pull-down control circuit provides beforehand cushioning by creating a protective discharge path before rapid clock signal transitions. This cushioning mechanism, activated by the stability pull-down control signal, absorbs and dissipates the voltage fluctuations caused by parasitic capacitor coupling during fast transitions, preventing glitch generation while maintaining high signal update speed.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses glitches caused by parasitic capacitors, ensuring the correctness of the gate driving signal waveform and preventing wrong charging of pixels, thereby improving the reliability of pixel operation.

Implementation Method 1

The first terminal of the capacitor C1 is coupled to the node QN, and the second terminal of the capacitor C1 is coupled the output terminal OUT

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

glitches caused by the coupling effect of parasitic capacitors of a transistor

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS9343178B2Gate driver and shift register

Publication Date: 2016.05.17 AU OPTRONICS CORP

AI summary

A gate driver has a plurality of shift registers. Each of the shift registers has at least three input terminals, two signal input terminals, a pull-up circuit, a driving circuit, a stability pull-down control circuit, and a stability pull-down circuit. The three input terminals of each shift register receive three different clock signals. Accordingly, the driving circuit and the stability pull-down control circuit of each shift register are controlled according to the three clock signals, such that a glitch causing by the coupling effect of the parasitic capacitor of the driving circuit is avoided and the stability of the gate driver is improved.