Shift Register Circuit for GOA Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The Gate Driver on Array (GOA) circuit in display technologies suffers from low signal drive capability and high power consumption due to issues with timely control of transistors and capacitors, leading to prolonged signal output times and increased energy usage.
Innovation Solution
A shift register circuit design incorporating specific control and output circuits, including switch transistors and capacitors, that rapidly control node voltages and maintain stable voltage differences, enabling timely switching and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the GOA circuit uses conventional transistor control mechanisms, then the circuit structure is simple, but the signal drive capability is low and power consumption is high
Solution Approach 1:
The patent implements dynamic control of transistor switching states through multiple clock signals (CLK1, CLK2) and control circuits. The transistors transition between on-state, off-state, and floating state dynamically, allowing the circuit to adapt its power consumption and drive capability based on operational requirements. This dynamic state management resolves the contradiction by enabling high drive capability only when necessary while reducing power consumption during steady states.
Solution Approach 2:
The patent changes the voltage parameters of nodes (first node, second node, third node) through controlled charging and discharging of capacitors. By adjusting voltage levels and timing sequences, the circuit achieves enhanced signal drive capability during output phases while maintaining lower power consumption during idle phases. The parameter changes in node voltages directly address the contradiction between drive capability and power consumption.
2Reliability
If the GOA circuit extends signal output time to ensure stable signal transmission, then signal reliability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clock signals (CLK1, CLK2) to control the switching sequences of transistors and the charging/discharging of capacitors. This periodic action ensures stable signal transmission through rhythmic refreshing of node voltages while limiting the duration of high-power output states. The periodic operation resolves the contradiction by maintaining reliability through regular signal renewal without requiring continuously extended output times.
Solution Approach 2:
The patent performs preliminary charging of capacitors connected to the first node and second node before actual signal output is needed. This preliminary action prepares the circuit for rapid, stable signal transmission while minimizing the duration of high-power consumption states. By pre-charging capacitors during low-power phases, the circuit achieves reliable signal output without extending the high-power output time.
3Productivity
If the GOA circuit increases transistor switching speed to improve drive capability, then signal transmission efficiency is improved, but control precision over node voltages decreases
Solution Approach 1:
The patent introduces capacitors as intermediary elements between the control circuits and the output nodes. These capacitors act as voltage buffers that smooth out rapid switching transitions, maintaining node voltage stability even during high-speed operation. The capacitors mediate between the fast switching required for high productivity and the voltage stability required for precise control, resolving the contradiction through their energy storage and release characteristics.
Solution Approach 2:
The patent implements feedback mechanisms through the control circuits that monitor the states of the first node, second node, and third node. The control circuits adjust switching sequences based on the current voltage states, ensuring precise control even during rapid transitions. This feedback control allows the circuit to maintain manufacturing precision while achieving high signal transmission efficiency through faster switching.
Data Source
AI summary
The disclosure discloses a shift register circuit, a method for driving the same, a gate drive circuit, and a display panel, and the shift register circuit includes: an input circuit, a first control circuit, a second control circuit, a third control circuit, a first output circuit, and a second output circuit, where the input circuit, the first control circuit, the second control circuit, the third control circuit, the first output circuit, and the second output circuit can cooperate with each other, thus shortening a period of time for pulling down the drive signal output terminal, improving a drive capability of the shift register circuit, and lowering power consumption of the shift register circuit.