Shift Register for GOA Circuit Stability

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Solution Overview

Problem

The Gate Driver on Array (GOA) circuit for display panels experiences instability due to competition between pull-up and pull-down nodes, affecting display quality.

Innovation Solution

A shift register design incorporating an input sub-circuit, first reset sub-circuit, pull-down sub-circuit, pull-down control sub-circuit, output sub-circuit, and second reset sub-circuit, which includes specific transistor configurations and voltage source connections to manage node levels and prevent competition between pull-up and pull-down nodes during dual scans.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a GOA circuit is used to drive gate lines, then the structure of the display panel is simplified, but the stability of GOA driving deteriorates due to competition between pull-up and pull-down nodes

Engineering Contradiction:
Improvestructure of display panelVSAvoidstability of GOA driving
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The shift register circuit is divided into multiple independent sub-circuits: input sub-circuit, first reset sub-circuit, output sub-circuit, pull-down sub-circuit, pull-down control sub-circuit, and second reset sub-circuit. Each sub-circuit has dedicated transistors and control terminals, separating the functions of pull-up and pull-down operations to eliminate mutual interference while maintaining the integrated GOA structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A pull-down control sub-circuit is introduced as an intermediary between the pull-up node and pull-down node. This control sub-circuit receives control signals from the input sub-circuit and regulates the pull-down operation timing, preventing direct competition between pull-up and pull-down nodes by coordinating their operations through intermediate control logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If pull-up and pull-down nodes operate simultaneously, then the shift register can perform dual scan functions, but competition between nodes causes poor stability and affects display quality

Engineering Contradiction:
Improvedual scan functionVSAvoidstability of GOA driving
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The circuit employs dynamic control of the pull-down node through the pull-down control sub-circuit, which adjusts the timing and duration of pull-down operations based on the state of the pull-up node. This dynamic coordination allows the circuit to adaptively manage simultaneous pull-up and pull-down operations, enabling dual scan functionality while preventing instability caused by node competition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The pull-down control sub-circuit is designed to activate pull-down operations at predetermined timing based on control signals received from the input sub-circuit. By preparing and executing pull-down actions in advance according to a controlled schedule, the circuit avoids conflicts with pull-up operations, ensuring stable dual scan performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11749155B2Shift register and driving method thereof, gate driving circuit
Publication Date: 2023.09.05 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US11749155B2 patent drawing
  • US11749155B2 patent drawing
  • US11749155B2 patent drawing

AI summary

Provided are a shift register, a driving method thereof, and a gate driving circuit. The shift register includes an input sub-circuit, a first reset sub-circuit, an output sub-circuit, a pull-down sub-circuit, a pull-down control sub-circuit, and a second reset sub-circuit. The input sub-circuit provides a signal of the first voltage source to the pull-up node and the first node under the control of the signal input terminal; the first reset sub-circuit provides a signal of the second voltage source to the pull-up node and the first node under the control of the reset terminal; the output sub-circuit outputs the signal of the clock signal terminal to the signal output terminal according to the level of the pull-up node.