Shift Register Unit for High-Level Pulse Output
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Solution Overview
Problem
Current display technologies face challenges in implementing a shift output of high-level signals using cascaded shift register units with P-type transistors, as the output terminal of a previous shift register unit outputs a high-level signal, preventing the next unit's output transistor from turning on in advance, thus hindering the shift output of high-level pulses.
Innovation Solution
A shift register unit is designed with an input circuit, a first control circuit, and an output circuit, where the input circuit controls a first control node based on an input signal and a clock signal, and the output circuit receives a voltage to output it to an output terminal, enabling the shift output of a level signal opposite to the turn-on voltage of a transistor, allowing for high-level signal output in cascaded units with P-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cascaded shift register units with P-type transistors are used, then the circuit can be integrated on the thin film transistor array substrate, but the output terminal of a previous unit outputs a high-level signal that prevents the next unit's output transistor from turning on in advance
Solution Approach 1:
The patent inverts the conventional shift register operation by enabling N-type transistor units to output low-level signals and P-type transistor units to output high-level signals. This inversion resolves the blocking issue where a high-level output from a P-type unit prevented the next unit's transistor from turning on, as the signal levels now complement each other in the cascade configuration
Solution Approach 2:
The patent changes the operating parameters of the shift register units by specifying that odd-numbered units use N-type transistors and even-numbered units use P-type transistors, with each type optimized for their respective signal levels. This parameter change allows proper signal propagation through the cascaded units while maintaining integration capability
2Stability of the object's composition
If the output terminal outputs a high-level signal, then the signal level is maintained, but the next unit's output transistor cannot turn on in advance
Solution Approach 1:
The patent implements periodic action through clock signal control, where transistors are turned on and off in alternating phases. The clock signal enables the output transistor to turn on in advance during specific phases, allowing the transistor to be prepared before the actual signal transition occurs, thus resolving the blocking issue while maintaining signal stability
Data Source
AI summary
A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes an input circuit, a first control circuit, and an output circuit. The input circuit is configured to receive an input signal and control a level of a first control node according to the input signal and in response to a first clock signal; the first control circuit is configured to control a level of a first node under control of the level of the first control node and the first clock signal; and the output circuit is configured to receive a first voltage of a first voltage terminal and output the first voltage to an output terminal under control of the level of the first node.