Shift Register Holding Circuit for GOA Leakage Prevention
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Solution Overview
Problem
The Gate Driver on Array (GOA) technology in display devices faces issues due to leakage current and parasitic capacitance in shift register units, leading to display abnormalities caused by abnormal turning on of transistors and incorrect scan signals.
Innovation Solution
A shift register unit is designed with a holding circuit that maintains the pull-up and pull-down nodes at specific levels during the V-blank time, preventing abnormal output of scan signals by using a second input signal to keep the nodes at low and high levels, respectively, thus preventing abnormal transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA technology is used in display devices, then integration is improved and cost is reduced, but leakage current and parasitic capacitance cause abnormal transistor turning on and display abnormalities
Solution Approach 1:
The holding circuit performs preliminary action by maintaining the pull-up node at low level and pull-down node at high level during V-blank time before the next scanning period begins. This preliminary state maintenance prevents leakage current and parasitic capacitance from causing abnormal transistor turning on, thereby resolving the reliability issue while preserving GOA technology integration benefits
Solution Approach 2:
The holding circuit applies preliminary anti-action by actively counteracting the harmful effects of leakage current and parasitic capacitance through controlled voltage levels on the pull-up and pull-down nodes. By maintaining opposite polarity levels during V-blank time, the circuit preemptively prevents the abnormal turning on that would otherwise occur, eliminating display abnormalities while keeping the integrated GOA structure
2Reliability
If holding circuit is added to maintain node levels during V-blank time, then display abnormalities are prevented, but device complexity increases
Solution Approach 1:
The holding circuit functionality is merged with the existing shift register unit structure. The holding circuit shares the same physical space and electrical nodes (pull-up node and pull-down node) within the shift register unit, combining the scanning function and holding function into a single integrated circuit block. This merging approach maintains scan signal accuracy while minimizing the increase in device complexity
Data Source
AI summary
The present disclosure relates to a shift register unit. The shift register unit includes a first input circuit configured to transmit a first voltage signal to a pull-up node, a pull-up circuit configured to transmit a first clock signal to a signal output terminal, a first pull-down control circuit configured to transmit a second clock signal to a pull-down node, a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node, a pull-up control circuit configured to transmit the second voltage signal to the pull-up node, a pull-down circuit configured to transmit the second voltage signal to the signal output terminal, and a holding circuit configured to maintain the pull-up node at a low level and/or maintain the pull-down node at a high level under control of a second input.