Shift Register Circuit With Independent Clock Signals
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Solution Overview
Problem
The driving capability of shift registers in scanning line driving circuits is hindered during display ineffective periods due to insufficient stepping up of the gate node, leading to reduced operational margin and high-speed operation limitations, especially when dealing with large load capacitance.
Innovation Solution
The implementation of a shift register circuit with additional transistors that allow the second clock signal to be activated independently, ensuring high driving capability regardless of the activation period of the first clock signal, by electrically separating the control electrodes and using multi-phase clock signals to maintain high transistor operation in both effective and ineffective display periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the first clock signal is deactivated in display ineffective periods to reduce power consumption, then power consumption is reduced, but the driving capability of the shift register is hindered due to insufficient stepping up of the gate node
Solution Approach 1:
The invention separates the clock signals into two independent phases: first clock signals for driving output transistors and second clock signals for driving transfer transistors. This segmentation allows independent control of each clock signal, enabling the first clock signal to be deactivated during display ineffective periods while the second clock signal remains active to maintain shift register operation and gate node charging capability.
Solution Approach 2:
The invention dynamically adjusts clock signal activation based on display requirements. During display effective periods, both first and second clock signals are activated for full driving capability. During display ineffective periods, only the second clock signal remains active, dynamically optimizing power consumption while maintaining necessary operational margin through the transfer transistor charging function.
2Reliability
If additional transistors are added to maintain driving capability during ineffective periods, then driving capability is improved, but device complexity increases
Solution Approach 1:
The transfer transistors controlled by second clock signals serve multiple functions: they transfer signals between stages during display effective periods and maintain charging capability during display ineffective periods. This multi-functionality allows the circuit to maintain driving capability without adding substantial complexity, as existing transfer transistor structures are utilized for dual purposes.
Solution Approach 2:
The invention changes the operational parameters by introducing a second clock signal with different activation timing compared to the first clock signal. This parameter change enables independent control of transfer transistor charging, maintaining gate node voltage levels during ineffective periods without requiring additional complex circuitry, simply by adjusting clock signal timing parameters.
Data Source
AI summary
An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).