Shift Register Initialization Circuit for Display Gate Drive
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Solution Overview
Problem
The gate drive circuit of display apparatuses often experiences erroneous operation due to internal nodes in shift register circuits being in an indefinite state, leading to abnormal image display.
Innovation Solution
A shift register circuit is designed with an initialization circuit to set a first node at an inactive potential, and control circuits to manage potentials based on input, reset, and clock signals, ensuring proper initialization and operation, including transistors and capacitors to maintain desired potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate drive circuit operates without initialization, then the circuit structure is simpler and operation is faster, but internal nodes may be in an indefinite state causing erroneous operation
Solution Approach 1:
The patent applies preliminary action by adding an initialization circuit that sets internal nodes to a predetermined state before the shift register circuit begins normal operation. This initialization occurs through a dedicated initialization pulse that activates the initialization circuit, ensuring nodes are in a defined state (e.g., first node at low level, second node at high level) before data input starts, thereby preventing erroneous operation without affecting the core shift register functionality
Solution Approach 2:
The patent uses an intermediary approach by introducing an initialization circuit as a separate functional block that mediates between the external initialization pulse and the internal nodes of the shift register. The initialization circuit includes transistors controlled by the initialization pulse to connect or disconnect power supply lines to internal nodes, acting as an intermediary mechanism that prepares the circuit state without interfering with normal operation once initialized
2Reliability
If an initialization circuit is added to set nodes to definite states, then operation reliability is improved, but the circuit structure becomes more complex
Solution Approach 1:
The initialization circuit is designed to perform preliminary state setting of internal nodes before normal operation begins. The circuit uses an initialization pulse to activate initialization transistors that set the first node to a low level and the second node to a high level through connections to power supply lines, ensuring reliable initialization without requiring complex continuous control mechanisms
Solution Approach 2:
The initialization circuit is designed to be self-activating through the initialization pulse, which automatically triggers the initialization process without requiring external control logic. The transistors in the initialization circuit are controlled by the initialization pulse itself, creating a self-service mechanism where the pulse both initiates and controls the initialization of internal nodes
3Reliability
If the first node is set to inactive potential during initialization, then erroneous operation is prevented, but the control circuit requires additional transistors and control signals
Solution Approach 1:
The first node is set to inactive potential (low level) as a preliminary action during initialization, before any data input occurs. The initialization pulse activates the initialization circuit to connect the first node to the low level power supply line through a transistor, ensuring the node starts in a defined inactive state, which prevents erroneous operation during the critical initialization period
Solution Approach 2:
The initialization process is implemented as a periodic action triggered by an initialization pulse that occurs at the beginning of operation or when needed. The pulse temporarily activates the initialization circuit to set the first node to low level, then deactivates, allowing the circuit to proceed with normal operation. This periodic initialization ensures reliability without requiring continuous control complexity
Data Source
AI summary
A shift register circuit is disclosed that includes an initialization circuit, a first node control circuit, a second node control circuit, and an output circuit. The initialization circuit is configured to set a first node to an inactive potential in response to an initialization pulse from an initialization terminal being active. The initialization pulse is immediately prior to an input pulse applied to an input terminal.