Shift Register Leakage Current Reduction via Input Node Potential Control

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Solution Overview

Problem

In OLED display devices, cascaded shift register units often experience leakage currents, which affect output signals and display quality due to excessive potential differences between transistor electrodes.

Innovation Solution

A shift register unit is designed with an adjustment circuit that couples or decouples the input signal terminal and input node based on the input signal potential, along with a voltage stabilizing circuit to maintain stable voltages and prevent leakage currents, comprising transistors and capacitors that manage potential differences across nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If cascaded shift register units are used to generate scan signals, then the display device can operate with integrated gate driving, but leakage current is generated due to excessive potential differences between transistor electrodes, affecting output signal and display effect

Engineering Contradiction:
Improveintegrated gate drivingVSAvoidleakage current
Core Design Contradiction:
Extent of automationVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a first transistor as an intermediary component between the input signal terminal and the input node. This first transistor acts as a mediator that controls the coupling between these two nodes, preventing direct harmful interactions and enabling isolated control of potential differences, thereby reducing leakage current while maintaining integrated gate driving functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically changes the potential at the input node by controlling the first transistor's switching state. By adjusting the potential difference between transistor electrodes through controlled coupling and decoupling of the input signal terminal, the system optimizes electrical parameters to minimize leakage current while preserving the automated scan signal generation capability

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If transistors are used to control signal transmission in the shift register unit, then signal routing and clocking can be achieved, but excessive potential differences between transistor electrodes cause leakage current

Engineering Contradiction:
Improvesignal routingVSAvoidoutput signal stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent segments the signal transmission path by introducing a first transistor that can independently control the coupling between the input signal terminal and the input node. This segmentation allows separate control of different signal paths, enabling reliable signal routing while managing potential differences to prevent leakage current that would compromise output signal stability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback control through the first transistor, which responds to the input signal potential to adjust the coupling state. This feedback mechanism dynamically optimizes the potential differences across transistor electrodes, ensuring reliable signal routing operations while preventing leakage current that would destabilize the output signal

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11348534B2Shift register unit and method for driving the same, and gate driving circuit
Publication Date: 2022.05.31 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11348534B2 patent drawing
  • US11348534B2 patent drawing
  • US11348534B2 patent drawing

AI summary

A shift register unit and a method for driving the same, and a gate driving circuit are provided. The shift register unit includes: an adjustment circuit coupled between an input signal terminal and an input node of the shift register unit, and configured to couple or decouple the input signal terminal and the input node under control of a potential at the input signal terminal; an input circuit for providing a potential at the input node to the pull-up node under control of a potential at the input signal terminal; an output circuit for receiving a clock signal from the clock signal terminal and provide an output signal to the output signal terminal based on the received clock signal under control of a potential at the pull-up node; and a control circuit for controlling a potential at the output signal terminal under control of a potential at the pull-up node.