Shift Register Isolation Circuit for Faster Gate-Line Charging
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Solution Overview
Problem
Conventional shift registers used in gate-line driving circuits for image display apparatuses face limitations in achieving high driving capability, which restricts their ability to charge gate lines at high speeds due to parasitic capacitance issues.
Innovation Solution
The introduction of a third transistor connected through a predetermined isolation circuit to the first transistor's control electrode, which electrically isolates the third and first nodes when the first node is at a higher potential, reducing parasitic capacitance and enhancing the step-up amount at the first node, thereby increasing the driving capability of the first transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a step-up capacitor is added between the gate and source of the first transistor to increase the gate-source voltage, then the driving capability of the first transistor increases, but the parasitic capacitance at the first node increases, which limits the step-up amount and reduces the charging speed of the gate line
Solution Approach 1:
The patent extracts the parasitic capacitance source (third transistor) from the first node by introducing an isolation circuit. This separates the harmful capacitive effect from the step-up node, allowing the step-up capacitor to increase driving capability without the penalty of accumulated parasitic capacitance from additional transistors connected directly to the first node.
Solution Approach 2:
The isolation circuit acts as an intermediary between the first node and the third transistor. It allows the third transistor to be part of the circuit while preventing its gate capacitance from directly adding to the parasitic capacitance at the first node, thus mediating the conflict between circuit functionality and parasitic effects.
2Adaptability or versatility
If more transistors are added to the circuit to improve functionality, then the circuit can perform additional functions, but the parasitic capacitance increases, which reduces the step-up amount and slows down the gate line charging speed
Solution Approach 1:
The patent extracts the capacitance contribution of the third transistor from the first node by using the isolation circuit. This allows the third transistor to be included in the circuit for functional purposes while its gate capacitance does not directly slow down the gate line charging speed through the first node.
Solution Approach 2:
The isolation circuit segments the circuit into isolated electrical domains. The third transistor operates in one domain while the first node operates in another, allowing multiple functions to coexist without their parasitic capacitances directly summing and degrading performance.
3Speed
If the step-up amount at the first node is increased to improve the driving capability, then the gate line can be charged faster, but the parasitic capacitance at the first node increases, which counteracts the step-up effect and reduces the net improvement
Solution Approach 1:
The patent converts the potentially harmful effect of the third transistor's gate capacitance into a beneficial configuration by using the isolation circuit. The third transistor is necessary for circuit functionality, but the isolation circuit ensures its capacitance does not harm the step-up process, effectively converting a harmful parasitic effect into a non-interfering configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for higher driving capability and faster charging of gate lines, improving the overall performance of the shift register and the image display apparatus.
Implementation Method 1
a parasitic capacitance (gate capacitance) of the third transistor does not contribute to a parasitic capacitance of the first transistor at the time of stepping up the first node
Data Source
AI summary
A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.