Shift Register Junction Voltage Control for TFT Lifespan
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Solution Overview
Problem
In liquid crystal displays, the high bias voltage at junctions between thin film transistors (TFTs) reduces the lifespan and stability of TFTs connected to these junctions due to prolonged ON states, affecting the overall performance of shift register units used in gate driving devices.
Innovation Solution
A shift register unit design that includes an input module for clock and frame signals, a processing module with TFTs to generate gate driving signals, and an output module to maintain at least one junction at a low level during specific frame intervals, reducing the high bias voltage exposure and incorporating a configuration where each shift register unit's output is connected to both previous and next units for signal transmission and resetting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TFTs are used to generate gate driving signals in shift register units, then the gate driving function is achieved, but the lifespan and stability of TFTs are reduced due to high bias voltage at junctions
Solution Approach 1:
The patent applies periodic action by alternating between two clock signals (first clock signal and second clock signal) in different frame intervals. During odd frame intervals, the first clock signal is active while the second is low; during even frame intervals, the second clock signal is active while the first is low. This periodic switching ensures that junctions experience high bias voltage only during specific intervals rather than continuously, thereby reducing cumulative stress on TFTs and improving their lifespan and stability.
2Productivity
If junctions are maintained at high level for long time to generate gate driving signals, then the driving signal generation is achieved, but the bias voltage on connected TFTs increases reducing their lifespan
Solution Approach 1:
The patent implements periodic action by designing the shift register to operate in alternating frame intervals with different clock signals. In odd frames, the first clock signal drives the circuit while the second clock signal is low; in even frames, the roles reverse. This periodic switching pattern allows the junctions to be at high level only during necessary intervals for signal generation, while maintaining low bias voltage during other intervals, thus balancing productivity with reduced stress duration on TFTs.
Solution Approach 2:
The patent applies parameter changes by dynamically switching between two different clock signal configurations. The first clock signal and second clock signal are alternated in a time-division manner, changing the operational parameters of the shift register unit periodically. This parameter switching allows the circuit to maintain signal generation capability while controlling the duration and intensity of bias voltage applied to TFTs, thereby extending their operational life.
Data Source
AI summary
A shift register unit includes an input module for inputting a second clock signal or a third clock signal, and for inputting a frame starting signal, a first clock signal, a low voltage signal, a reset signal as well as a first signal and a second signal transmitted from a next neighboring shift register unit; a processing module for generating a gate driving signal and allowing a level of at least one of first junctions formed by at least two TFTs to be maintained at low level in a frame interval during which the second clock signal or the third clock signal inputted from the input module is maintained at low level; and an output module for transmitting the gate driving signal generated by the processing module.