Shift Register Latch Clock Generation for Multiphase Skew Compensation
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Solution Overview
Problem
Shift registers operating with multiphase internal clock signals face challenges in maintaining stable operation due to potential skews in clock signal periods, which can disrupt the synchronization and accuracy of control signal shifting.
Innovation Solution
The proposed shift register design includes a latch clock generation circuit that generates latch clock signals and inverted latch clock signals based on multiple internal clock signals, allowing for synchronization with selected clock edges to produce a stable shift control signal, even in the presence of skew between clock signals, using NAND and NOR logic operations and D-flipflop configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shift registers operate with multiphase internal clock signals to improve operation speed, then productivity is improved, but clock signal skew causes instability in control signal shifting
Solution Approach 1:
The patent introduces a latch clock signal as an intermediary between the multiphase internal clock signals and the control signal latching mechanism. This latch clock signal is generated by combining multiple internal clock signals through logic circuits (NAND/NOR gates), thereby mediating the clock distribution to eliminate the harmful effects of clock skew while preserving the speed benefits of multiphase clocks
2Productivity
If multiple internal clock signals are used to increase operation speed, then productivity is improved, but device complexity increases due to additional clock signal management
Solution Approach 1:
The patent merges multiple internal clock signals and their inverted versions through logic circuits to generate the latch clock signal. By combining these signals using NAND and NOR gates, the system reduces clock signal management complexity while maintaining the speed advantages of multiphase clocking
Data Source
AI summary
A shift register includes a latch clock generation circuit and a clock latch circuit. The latch clock generation circuit generates a latch clock signal and an inverted latch clock signal based on a first internal clock signal, a first inverted internal clock signal, a second internal clock signal, and a second inverted internal clock signal. The clock latch circuit latches a control signal in synchronization with one signal selected from the first internal clock signal, the first inverted internal clock signal, the second internal clock signal, and the second inverted internal clock signal. The clock latch circuit also latches the latched control signal in synchronization with the latch clock signal or the inverted latch clock signal to generate and output a shift control signal.