Shift Register Circuit for Compact LCD Driving

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Solution Overview

Problem

Existing liquid crystal display technologies face challenges in efficiently driving small-sized liquid crystal panels with limited space, requiring a compact and power-efficient driving circuit that can ensure normal operation and sequential scanning of data signals.

Innovation Solution

A shift register with an input circuit and an output control circuit, composed of transistors, is designed to transmit signals under control of clock signals, allowing for delayed signal output to the next row, reducing the number of transistors and power consumption while simplifying the driving circuit structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a conventional driving circuit is used for small-sized liquid crystal panels, then the display can be driven, but the circuit occupies excessive space and consumes high power

Engineering Contradiction:
Improvedriving circuit areaVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent merges the input circuit and output control circuit into a single integrated shift register unit, sharing common transistors (M1-M6) and power terminals between input signal transmission and output signal control functions. This consolidation reduces the total number of transistors required compared to conventional separate circuit designs, thereby reducing both the driving circuit area and power consumption while maintaining proper sequential scanning operation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shift register circuit performs multiple functions using the same components: the input circuit transmits input signals to the output control circuit, the output control circuit generates output signals for current row scanning, and simultaneously delays signals for next row scanning. This multi-functionality reduces the overall circuit complexity and component count, addressing the space and power constraints in small-sized display devices.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If the number of transistors is reduced to save space and power, then manufacturing cost decreases, but circuit functionality may be compromised

Engineering Contradiction:
Improvenumber of transistorsVSAvoidcircuit functionality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent combines input and output control functions into a single shift register unit with shared transistors M1-M6, reducing the total transistor count while maintaining all necessary functions: input signal reception, output signal generation for current row, and delayed signal transmission for next row scanning.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shift register is segmented into distinct functional blocks (input circuit with transistors M1-M6, output control circuit with transistors M7-M14, and inter-row delay path) that can be independently analyzed and verified, ensuring that functionality is preserved while reducing overall complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10515603B2Shift register, driving method, gate driving circuit, and display device
Publication Date: 2019.12.24 BOE TECHNOLOGY GROUP CO LTD
  • US10515603B2 patent drawing
  • US10515603B2 patent drawing
  • US10515603B2 patent drawing

AI summary

A shift register, a driving method, a gate driving circuit, and a display device are provided. The shift register includes an input circuit and an output control circuit. The input circuit transmits a first signal from a first power terminal or a second signal from a second power terminal to the output control circuit under control of an input signal, a first clock signal and a second clock signal. The output control circuit transmits the first signal from the first power terminal or the second signal from the second power terminal to a signal output terminal under control of the first clock signal and the second clock signal. The input signal input to the shift register is delayed and output to a signal input terminal of a shift register in a next row.