Shift Register for LCD Gate Line Voltage Symmetry
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Solution Overview
Problem
In liquid crystal display (LCD) devices, parasitic capacitance and RC delay cause differences in pixel electrode waveforms between the proximal and distal ends of a gate line, leading to asymmetric data voltages and flickering issues due to varying feedthrough voltages, which affect display quality.
Innovation Solution
A shift register with specific sub-circuits and transistors is designed to output a voltage that reduces the difference in gate line driving voltage changes between the proximal and distal ends, using a first output sub-circuit to output a high level and a second output sub-circuit to output a lower voltage in a time-share manner, ensuring symmetry of data voltages about a common voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional shift register is used to drive gate lines, then the circuit structure is simple, but the feedthrough voltages at proximal and distal ends become asymmetric due to parasitic capacitance and RC delay
Solution Approach 1:
The patent introduces a dual-output shift register that dynamically switches between two output modes: a conventional high-level output and a low-voltage output. By adjusting the output voltage level according to the position along the gate line (proximal vs distal end), the system compensates for RC delay effects and achieves symmetric feedthrough voltages without significantly increasing circuit complexity
Solution Approach 2:
The patent changes the voltage parameter of the gate line driving signal by providing two different output voltage levels. The low-voltage output mode uses a reduced voltage level to compensate for the voltage drop caused by RC delay at distal ends, thereby achieving symmetric feedthrough voltages and improving waveform symmetry
2Power
If the gate line driving voltage is increased to compensate for RC delay, then the driving capability is improved, but the difference in feedthrough voltages between proximal and distal ends increases
Solution Approach 1:
The patent applies different voltage levels to different segments of the gate line. The low-voltage output mode is specifically applied to distal ends where RC delay effects are more pronounced, while the conventional high-level output is used for proximal ends. This localized approach achieves voltage symmetry without excessive overall voltage increase
3Productivity
If asymmetric feedthrough voltages occur due to RC delay, then the gate line can be driven, but data voltage symmetry is lost causing flickering
Solution Approach 1:
The patent implements a feedback mechanism where the output voltage level is adjusted based on the detected or calculated RC delay characteristics of the gate line. By monitoring the voltage drop and timing effects, the system dynamically selects between high-level and low-voltage output modes to maintain symmetric feedthrough voltages and eliminate flickering
Data Source
AI summary
A shift register includes a first input sub-circuit, a first output sub-circuit, and a second output sub-circuit. The first input sub-circuit is connected to a first input terminal, a pull-up node, and a first control terminal, and the first input sub-circuit is configured to output a voltage of the first control terminal to the pull-up node under control of a voltage of the first input terminal. The first output sub-circuit is connected to the pull-up node, a clock signal terminal, and an output terminal, and the first output sub-circuit is configured to output a first level of the clock signal terminal to the output terminal under control of a voltage of the pull-up node. The second output sub-circuit is connected to the output terminal, a second output control terminal, and a first voltage terminal, and the second output sub-circuit is configured to output a voltage of the first voltage terminal to the output terminal under control of a voltage of the second output control terminal.