Shift Register Leakage Current Reduction
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Solution Overview
Problem
Display devices face challenges in reducing power consumption while maintaining high definition, as PMOS transistors in pixel driving circuits experience leakage currents, leading to image flicker and poor display quality, especially at low frame rates.
Innovation Solution
A shift register design that enables cascade shifting of high-level and low-level signals without loss, allowing complete transistor turn-off and reducing leakage current, by using a specific configuration of control modules and coupling modules in the shift register circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PMOS transistors are used in pixel driving circuits, then stable display can be ensured, but leakage current occurs leading to image flicker and poor display quality
Solution Approach 1:
The patent changes the electrical parameters of the pixel driving circuit by substituting PMOS transistors with NMOS transistors and implementing a dual-output shift register with complementary signaling. This parameter change eliminates leakage current while maintaining display stability through improved signal control mechanisms.
Solution Approach 2:
The shift register is segmented into dual outputs (first and second output ends) that provide complementary high-level and low-level signals. This segmentation allows independent control of signal paths, enabling complete transistor turn-off and elimination of leakage current while maintaining stable display operation.
2Loss of information
If PMOS shift is used in traditional shift registers, then high-level shifting includes step-down, but high-level cannot be shifted effectively without loss
Solution Approach 1:
The patent inverts the traditional PMOS shift approach by implementing NMOS-based shifting with complementary high-level and low-level signal outputs. This inversion eliminates the step-down problem by providing full-swing signals that can be shifted effectively without loss, while the dual-output structure simplifies the shifting mechanism.
Solution Approach 2:
The shift register is designed with multi-functionality to output both high-level and low-level signals simultaneously through different output ends. This universal design allows the same circuit to drive different types of transistors (PMOS or NMOS) in the next stage, eliminating signal loss while maintaining manageable complexity.
3Object-generated harmful factors
If transistors cannot be turned off completely, then leakage current still exists, but display effect is affected
Solution Approach 1:
The patent introduces an intermediary mechanism through the dual-output shift register that provides complementary signaling. This intermediary structure ensures complete transistor turn-off by using the second output end to provide opposite polarity signals that fully disable transistor conduction, eliminating leakage current while improving display effect.
Solution Approach 2:
The shift register employs periodic action through clocked signaling that alternates between high-level and low-level states. This periodic control ensures transistors are completely turned off during appropriate phases, eliminating leakage current while maintaining reliable display operation through rhythmic signal regeneration.
Data Source
AI summary
Disclosed are a shift register, gate electrode driving circuit, display panel and display device. The shift register includes a second output module and a coupling module, the coupling module having two ends electrically connected to a third node and a second signal output end respectively. In a second phase, a potential at a fourth node is an enable level, the second output module transfers a high-level signal at a first power source signal input end to a second output end; in a third phase, a potential at the third node is the enable level, the second output module transfers a low-level signal at a second power source signal input end to the second output end; the low-level signal at the second output end is coupled to the third node through a coupling function of the coupling module, the potential at the third node is then lower in the third phase than in the second phase.