Shift Register Unit Leakage Suppression for Ultra-Low Refresh Displays
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Solution Overview
Problem
Conventional gate drive circuits generate significant noise at ultra-low refresh rates due to electricity leakage, affecting display quality and increasing power consumption.
Innovation Solution
A shift register unit with an input circuit, first and second control circuits, and an output circuit is designed to suppress leakage by controlling signal flow through multiple clock and power supply terminals, ensuring stable output signals for low-frequency driving of pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the refresh rate is reduced to ultra-low frequency (e.g., 1 Hz) to reduce power consumption, then power consumption is reduced, but output noise increases significantly due to electricity leakage
Solution Approach 1:
The shift register unit is divided into multiple functional modules: input circuit, first control circuit, second control circuit, and output circuit. Each module handles specific signal processing tasks, allowing precise control of signal flow and leakage suppression at different stages, thereby reducing output noise while maintaining ultra-low refresh rate operation
Solution Approach 2:
Multiple clock signal terminals (first, second, third, fourth clock signal terminals) and control nodes act as intermediaries to precisely control signal transmission timing. These intermediaries enable the circuit to distinguish between valid signal periods and idle periods, suppressing leakage during idle periods while maintaining signal integrity during active periods
Solution Approach 3:
The circuit dynamically changes its operational parameters based on clock signal phases and control node states. By adjusting the timing and duration of signal transmission through multiple clock cycles and control signals, the circuit optimizes power consumption while minimizing leakage-induced noise at ultra-low refresh rates
2Use of energy by moving object
If conventional gate drive circuits are used to drive pixels at ultra-low refresh rates, then power consumption is reduced, but display quality deteriorates due to large output noise
Solution Approach 1:
The output circuit is designed with preliminary anti-leakage measures that actively counteract electricity leakage before it can affect the output signal. By preemptively controlling signal levels and timing through multiple clock signal terminals, the circuit prevents leakage-induced noise from degrading display quality while maintaining ultra-low power consumption
Solution Approach 2:
The shift register unit employs dynamic control through multiple clock signal terminals and control nodes that adaptively adjust signal transmission based on operational requirements. This dynamic approach allows the circuit to optimize the balance between power consumption and output signal quality, ensuring reliable display performance at ultra-low refresh rates
Data Source
AI summary
A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.