Shift-Register Capacitor Oscillator for Linear Frequency Sweeps
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Solution Overview
Problem
Existing oscillators generating frequency sweeps face challenges in achieving high accuracy and linearity while maintaining low circuit complexity, particularly in biomedical applications, where they often require fine resolution, wideband linear frequency modulation, and efficient use of circuit area and power.
Innovation Solution
The use of a shift register controlled by a clock signal with time modulation to connect or disconnect capacitors in a predetermined order, allowing for intrinsic frequency dependence on the number of capacitors, which compensates for non-linearities and reduces circuit complexity by minimizing control lines and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of capacitors are used to achieve desired resolution performance in a DCO, then manufacturing precision is improved, but device complexity increases due to the complexity of addressing through row-column decoding
Solution Approach 1:
The patent segments the capacitor control into individual bit positions within a shift register, where each bit controls a specific capacitor. This segmentation allows independent addressing of each capacitor through simple bit shifting operations, eliminating the need for complex row-column decoding while maintaining fine resolution control over the oscillator frequency.
Solution Approach 2:
The patent employs a dynamic shift register that can shift bits left or right to dynamically add or remove capacitors from the circuit. This dynamic control mechanism allows the oscillator to transition between different frequency states by simply shifting the bit pattern, replacing static row-column decoding with a flexible, time-based control approach that reduces complexity.
2Manufacturing precision
If pre-distortion in the frequency domain is used to handle non-linearities due to inverse square-root dependence of frequency on capacitance, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Instead of applying pre-distortion to the frequency output to correct non-linearities, the patent inverts the approach by applying non-linear time modulation to the capacitor switching sequence. By controlling the timing of capacitor addition/removal in a non-linear fashion, the resulting frequency sweep becomes linear, eliminating the need for complex frequency-domain pre-distortion circuits.
Solution Approach 2:
The patent changes the time parameter of capacitor switching from uniform intervals to non-uniform intervals that compensate for the inverse square-root relationship between frequency and capacitance. By adjusting the timing parameter of when each capacitor is switched, the system achieves linear frequency sweeps without requiring additional pre-distortion hardware or complex control logic.
3Ease of operation
If capacitors are switched at regular time intervals, then ease of operation is improved, but manufacturing precision deteriorates due to non-linear frequency sweep resulting from inverse square-root dependence
Solution Approach 1:
The patent modifies the time parameter of capacitor switching from constant intervals to variable intervals that follow a specific non-linear pattern. This parameter change in the switching timing compensates for the inverse square-root relationship between capacitance and frequency, producing a linear frequency sweep while maintaining the simplicity of systematic capacitor control through shift register operations.
4Manufacturing precision
If row-column decoding is used to control a large number of capacitors, then manufacturing precision is improved, but loss of time increases due to slow switching speed
Solution Approach 1:
The patent replaces the static, multi-stage row-column decoding process with a dynamic shift register that can rapidly shift bits across all capacitor control lines in a single clock cycle. This dynamic approach allows all capacitors to be switched simultaneously or in rapid succession, dramatically increasing switching speed while maintaining the ability to precisely control each individual capacitor for fine frequency resolution.
Data Source
AI summary
An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.