Shift Register Topology for Low-Amplitude Clock Operation
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Solution Overview
Problem
Conventional shift registers face issues with increased occupation area, reduced frequency properties due to delayed waveforms, and higher power consumption, especially when using level shifters in external or internal circuits, and are affected by transistor threshold voltage fluctuations, leading to inaccurate operations with small amplitude signals.
Innovation Solution
A shift register design that operates without level shifters by utilizing a configuration of multiple clocked inverters connected in a specific manner to manage clock signals and power sources, ensuring accurate operation with small amplitude signals and reducing unintended current flow, thereby minimizing area occupation and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level shifter is arranged in the internal circuit to operate the internal circuit with accuracy using a signal having amplitude of about 3V, then the operation accuracy is improved, but the occupation area of the driver circuit increases, frequency property is reduced due to delayed waveforms, and power consumption increases
Solution Approach 1:
The invention extracts and eliminates the level shifter component from the internal circuit by redesigning the clocked inverter structure. The clocked inverter is modified to directly accept small amplitude clock signals (about 3V) without requiring level shifting, thereby removing the source of waveform delay and reducing occupation area while maintaining operation accuracy through the redesigned transistor configuration and power source connection method
Solution Approach 2:
The invention changes the operating parameters of the clocked inverter by modifying how power sources are connected to the transistors. Specifically, the n-channel transistor source is connected to VSS and the p-channel transistor source is connected to VDD, allowing the circuit to operate directly with small amplitude clock signals. This parameter change eliminates the need for level shifting while maintaining accurate operation
2Reliability
If a level shifter is arranged in the external circuit to operate the internal circuit with accuracy, then the operation accuracy is improved, but the total size of the casing increases, manufacturing cost increases, and power consumption increases
Solution Approach 1:
The invention extracts the level shifting function from the external circuit by integrating level shifting capability directly into the clocked inverter structure. The modified clocked inverter can directly process small amplitude clock signals from external circuits without requiring separate level shifter components, thereby reducing the total device size and eliminating additional power consumption while maintaining operation accuracy
3Use of energy by moving object
If the amplitude of the clock signal is made smaller than the potential difference between VDD and VSS to reduce power consumption, then power consumption is reduced, but the transistor cannot be turned OFF completely due to threshold voltage, causing through current and false operation
Solution Approach 1:
The invention changes the voltage reference parameters by connecting the n-channel transistor source to VSS and the p-channel transistor source to VDD. This parameter change allows the transistors to switch reliably even with small amplitude clock signals because the gate-to-source voltage swing is sufficient to overcome threshold voltages when referenced to the appropriate power sources, eliminating through current while maintaining low power consumption
4Area of moving object
If a current driving type of shift register is used to operate without level shifting, then the occupation area is reduced, but fluctuation in TFT characteristics between adjacent TFTs causes inaccurate operation
Solution Approach 1:
The invention applies local quality by making each clocked inverter stage self-adjusting to local variations in TFT characteristics. The dual-transistor configuration with separate VDD and VSS connections creates local voltage references that compensate for adjacent TFT fluctuations, allowing accurate operation without level shifting while maintaining compact size
Data Source
AI summary
The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n−1)-th stage operates in accordance with the first output from the previous stage, an output from the second clocked inverter at the previous stage, and the first CK signal; the second clocked inverter at the (2n−1)-th stage operates in accordance with the second output from the previous stage, an output of the first clocked inverter at the (2n−1)-th stage, and the first CK signal; one of the first output and the second output is equal to a potential of VDD and the other is equal to a potential of VSS; the first CK signal at the 2n-th stage operates the third output from the (2n−1)-th stage, an output of the second clocked inverter and the second CK signal; the second clocked inverter at the 2n-th stage operates in accordance with the fourth output from the (2n−1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second CK signal; one of the third output and the fourth output is equal to the potential of VDD and the other is equal to the potential of VSS, and the second CK signal is an inversion signal of the first CK signal and the amplitude of the CK signal is smaller than the power supply potential.