Shift Register Power Reduction in Low-Frequency Display Modes
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Solution Overview
Problem
Display apparatuses face high power consumption even in low-frequency display modes due to active shift register circuits, which do not fully utilize the power-saving potential of low-frequency operation.
Innovation Solution
A shift register design with cascaded circuits that includes control modules to manage clock signals and output signals, allowing for effective pulses during data writing and an ineffective fixed level during retention phases to reduce unnecessary charging and discharging, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the shift register circuit operates continuously in normal working state, then the display panel can maintain stable signal output, but the power consumption increases significantly in low-frequency display mode
Solution Approach 1:
The shift register circuit dynamically adjusts its operating state based on display mode requirements. In low-frequency display mode, the circuit transitions from continuous operation to periodic operation, where it alternates between active signal output phases and idle retention phases. This dynamic state adjustment allows the circuit to maintain signal stability when needed while reducing power consumption during retention periods by minimizing unnecessary charging and discharging operations.
Solution Approach 2:
The patent implements periodic action by dividing the operation into distinct phases: data writing phases where the third clock signal contains effective pulses for signal transmission, and retention phases where the third clock signal is set to an ineffective fixed level to minimize power consumption. This periodic alternation between active and idle states allows the shift register to maintain display functionality while significantly reducing power consumption during low-frequency operation.
2Measurement precision
If the third clock signal continuously provides effective pulses, then the shift register can accurately output signals, but unnecessary charging and discharging occurs during retention phases increasing power consumption
Solution Approach 1:
The patent applies local quality by differentiating the characteristics of the third clock signal based on the operational phase. During data writing phases, the third clock signal contains effective pulses with specific characteristics to ensure accurate signal output. During retention phases, the third clock signal is modified to an ineffective fixed level, changing its local quality to minimize power consumption. This localized adjustment of signal characteristics allows the circuit to optimize both accuracy and energy efficiency for different operational requirements.
3Productivity
If the shift register operates at high frequency, then display resolution and quality improve, but power consumption increases
Solution Approach 1:
The shift register implements dynamic frequency adjustment by adapting its operating frequency to the display mode requirements. In high-frequency display modes, the circuit operates with continuous effective clock pulses to maintain high refresh rates and display quality. In low-frequency display modes, the circuit dynamically reduces its operating frequency by extending retention phases where the third clock signal is held at an ineffective fixed level, thereby significantly reducing power consumption while maintaining acceptable display performance.
Data Source
AI summary
A shift register includes a plurality of cascaded shift register circuits. The first control module of a shift register circuit controls the potential of a first node according to a first clock signal, a second clock signal, and the potential of the first node. A second control module controls the potential of a second node according to the first level signal of a third clock signal and the potential of the first node. An output module controls, according to the potential of the first node, the time of outputting the first level signal and controls, according to the potential of the second node, the time of outputting a second level signal. In a data writing phase, the third clock signal includes a plurality of effective pulses. In at least in a first retention frame, the third clock signal is an ineffective fixed level.