Shift Register Holding Circuit for Low-Frequency Display Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices consume significant power even in low-frequency modes due to continuous operation of shift registers, failing to fully utilize the potential power savings in low-frequency display modes.
Innovation Solution
A shift register design with an input module, control module, and output module, incorporating switch units and energy storage units, controls potential states to maintain consistency during low-frequency holding stages, reducing unnecessary charging and discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the shift register operates continuously in normal mode, then the display function is maintained, but the power consumption increases during low-frequency holding stages
Solution Approach 1:
The shift register operates in two dynamic modes: normal operation mode for active display and low-power holding mode for standby. The circuit dynamically switches between these modes based on display requirements, allowing the shift register to adapt its operational state and reduce power consumption during holding stages while maintaining display functionality when needed.
Solution Approach 2:
The patent changes the operational parameters of the shift register by controlling the switch units to different states. During holding stages, the switch units are controlled to disconnect the clock signal input, changing the operational parameter from active clocked operation to static holding state, thereby reducing power consumption while preserving the stored signal state.
2Measurement precision
If the switch units frequently switch states to maintain signal integrity, then the signal accuracy is improved, but the energy loss increases due to repeated charging and discharging
Solution Approach 1:
Instead of continuous switching, the patent implements periodic action by maintaining the switch units in stable states during holding periods. The switches only change state when transitioning between normal operation and holding modes, not continuously during the holding stage, thereby reducing energy loss from frequent charging and discharging while maintaining signal integrity through periodic stabilization.
Data Source
AI summary
Shift register, gate driving circuit and driving method thereof, and display panel are provided. The shift register includes input module, control module and output module. A control terminal of the input module is configured to receive first clock signal. The control module includes first switch unit, second switch unit, and energy storage unit. A control terminal of the first switch unit is configured to receive first control signal. A control terminal of the second switch unit is configured to receive second control signal. A first terminal of the second switch unit is configured to receive second power signal. A second terminal of the energy storage unit is configured to receive second clock signal. Input terminals of the output module are respectively configured to receive the second clock signal, the first power signal and the second power signal. An output terminal of the output module is configured to output scanning signal.