Shift Register Low Power Consumption
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Solution Overview
Problem
Existing shift registers in LCDs face high power consumption due to large amorphous silicon (a-Si) thin film transistors, which increase parasitic capacitance and dynamic power consumption, necessitating a solution to minimize power usage while maintaining reliable operation.
Innovation Solution
A shift register design with multiple stages connected in series, utilizing a pull-up and pull-down circuit configuration with thin film transistors driven by a DC voltage signal, reducing channel width and dynamic power consumption, and incorporating capacitors and control circuits to manage signal transmission efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large a-Si TFTs are used to drive gate lines, then the driving capability is improved, but the parasitic capacitance and power consumption increase substantially
Solution Approach 1:
The shift register is divided into multiple stages (first stage, second stage, etc.), with each stage independently driving a portion of the gate lines. This segmentation allows the use of smaller TFTs in each stage while collectively maintaining the driving capability for the entire display panel, thereby reducing parasitic capacitance and power consumption compared to using a single large TFT.
Solution Approach 2:
The invention introduces a vertical stacking dimension by placing the shift register stages along a side of the display panel rather than horizontally across the entire panel. This dimensional reorganization allows the gate driver to be integrated in a compact form factor, enabling the use of smaller TFTs while still achieving sufficient driving capability through the staged architecture.
2Reliability
If a-Si TFTs with large channel width are used, then the mobility compensation is improved, but the parasitic capacitance increases
Solution Approach 1:
Each stage of the shift register is designed with locally optimized TFT dimensions and configurations tailored to its specific driving requirements. Rather than using uniformly large TFTs across all stages, each stage uses appropriately sized TFTs that provide sufficient mobility compensation for its portion of the load, thereby reducing overall parasitic capacitance while maintaining reliability.
Solution Approach 2:
The shift register employs dynamic control mechanisms including clock signals and control nodes that adjust the operating characteristics of TFTs in real-time. This dynamic operation allows smaller TFTs to achieve equivalent mobility compensation performance by optimizing switching timing and voltage levels, thereby reducing parasitic capacitance without sacrificing reliability.
3Speed
If clock signals are used to control output transistors, then the signal transmission is improved, but the dynamic power consumption increases
Solution Approach 1:
The shift register uses periodic clock signals to control the sequential operation of each stage, enabling efficient signal transmission through the staged architecture. The periodic timing allows each stage to operate only when needed, reducing overall dynamic power consumption compared to continuous operation, while maintaining high-speed signal transmission through synchronized clocking.
Solution Approach 2:
Each stage of the shift register is designed to automatically advance the signal to the next stage through the clocked architecture, reducing the need for additional active control elements that would increase power consumption. The self-advancing nature of the staged design maintains fast signal transmission while minimizing energy loss through efficient signal propagation.
Data Source
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AI summary
A shift register (100) comprises a plurality of stages (S). In one embodiment, each stage (S) includes a first output (111), a second output (112), a pull-up circuit (120) electrically coupled between a node (Q) and the second output (112), a pull-up control circuit (130) electrically coupled to the node (Q), a pull-down control circuit (150) electrically coupled between the node (Q) and the first output (111), and a control circuit (140) electrically coupled to the node (Q) and the first output (111). Each stage comprises separate pull-up transistors (T21,T22) for driving the first output (111) and for providing a carry signal (ST) to a subsequent stage through the second output (112).