Shift Register Memory Data Distribution via Diagonal ECC
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Solution Overview
Problem
Shift register memories, particularly magnetic domain wall memories, face challenges in maintaining data reliability due to biased error rates and burst errors across layers, leading to inefficient data storage and retrieval operations.
Innovation Solution
The implementation of a memory system that uses a combination of error correction code frames, including diagonal and row ECC frames, to evenly distribute data across layers and magnetic memory lines, ensuring balanced error correction and improved data reliability through diagonal and product code arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in shift register memory layers, then storage capacity is improved, but biased error rates and burst errors increase across layers
Solution Approach 1:
The patent segments data into multiple error correction code frames (ECC frames) and distributes them across different layers and magnetic memory lines. Each ECC frame contains a portion of the data and corresponding error correction information, allowing independent error correction for each segment. This segmentation prevents burst errors from affecting the entire data set and enables targeted recovery of corrupted segments.
Solution Approach 2:
The patent introduces diagonal ECC frames that extend across multiple layers in a diagonal pattern, adding a new dimension to error correction. This diagonal arrangement allows error correction to operate not only within individual layers but also across layer boundaries, effectively handling errors that propagate through the stack direction and providing three-dimensional error protection.
2Reliability
If error correction code frames are used to distribute data evenly, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal error correction framework where the same ECC frame structure and correction mechanisms are applied across all layers and data types. The diagonal and row ECC frames use consistent encoding and decoding procedures, allowing the memory system to handle errors uniformly regardless of which layer or line is affected, simplifying control logic while maintaining comprehensive protection.
Solution Approach 2:
The patent applies error correction codes in advance during the data writing process, embedding correction information within each ECC frame before data is stored in the shift register memory. This preliminary encoding ensures that error correction capability is already in place when data is read, eliminating the need for complex real-time correction mechanisms and simplifying the read operation.
Data Source
AI summary
A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.