Phase-Shifted Shift Register to Eliminate LCD Multi-Output

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Solution Overview

Problem

The existing shift registers in LCD devices suffer from a multi-output issue due to a coupling phenomenon, which deteriorates the picture quality by causing the enable node to be charged undesirably and leading to multiple output pulses during one frame.

Innovation Solution

A shift register design that incorporates at least two clock transmission lines with phase differences and includes a noise eliminating unit to prevent undesired charging by supplying a start pulse or output signal from the preceding stage to the enable node in response to a second clock pulse with a prior phase, ensuring proper timing and discharge of the enable node.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single clock transmission line is used to drive the pull-up switching unit, then the circuit structure is simple, but the enable node is undesirably charged due to coupling phenomenon causing multi-output

Engineering Contradiction:
Improvecircuit structureVSAvoidoutput stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The single clock transmission line is segmented into two separate clock transmission lines (first and second clock transmission lines) that transmit clock pulses with different phases. This segmentation prevents the coupling phenomenon from charging the enable node undesirably, thereby eliminating the multi-output issue while maintaining circuit functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The noise eliminating unit is activated in advance to prevent the coupling phenomenon from occurring. By detecting the clock pulse from the second clock transmission line and actively discharging the enable node before the harmful charging can occur, the system prevents the multi-output problem before it manifests.

Inventive Principle:
Principle #9Preliminary anti-action

2Productivity

If the enable node is allowed to charge freely during clock pulse transmission, then the pull-up switching unit can output pulses, but the coupling phenomenon causes undesired charging leading to multiple outputs per frame

Engineering Contradiction:
Improvepulse output capabilityVSAvoidoutput precision
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The noise eliminating unit operates based on feedback from the second clock transmission line. When a clock pulse is detected on the second clock line, the noise eliminating unit activates to discharge the enable node, creating a feedback mechanism that precisely controls the enable node's charge state and prevents multi-output while maintaining proper pulse output capability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The noise eliminating unit acts as an intermediary between the clock transmission lines and the enable node. It mediates the interaction by selectively discharging the enable node in response to the second clock pulse, preventing the direct harmful coupling effect from causing multi-output while allowing legitimate pulse transmission to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7738622B2Shift register
Publication Date: 2010.06.15 LG DISPLAY CO LTD
  • US7738622B2 patent drawing
  • US7738622B2 patent drawing
  • US7738622B2 patent drawing

AI summary

A shift register is disclosed, which can prevent a multi-output caused by a coupling phenomenon, the shift register comprising at least two clock transmission lines which transmit at least two clock pulses provided with the phase difference; and a plurality of stages which are supplied with the clock pulses from the clock transmission lines, and output output-signals in sequence, wherein each of the stages comprises a pull-up switching unit which is supplied with the first clock pulse, and outputs the first clock pulse as the output-signal according to a signal state of an enable node; and a noise eliminating unit which responds to the second clock pulse of which phase is prior to that of the first clock pulse supplied to the pull-up switching unit, and supplies a start pulse externally provided or the output-signal provided from the preceding stage to the enable node.