Shift Register Multi-Output Circuit Narrow Bezel Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In display technologies, the existing gate driver circuits with cascaded shift registers occupy a large area due to each shift register being able to scan only one gate line, which hinders the achievement of a narrow bezel design for high-resolution display devices.
Innovation Solution
A shift register design that includes an output sub-circuit, a cascade sub-circuit, and additional output sub-circuits, where the output sub-circuit transmits a first clock signal to scan a gate line, the cascade sub-circuit transmits a second clock signal, and additional output sub-circuits transmit clock signals to multiple gate lines under the control of the cascade node, allowing for the scanning of multiple gate lines with fewer shift registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If each shift register scans only one gate line, then the gate driver circuit can be simply designed, but the area occupied by the gate driver circuit becomes large
Solution Approach 1:
The shift register is designed with multiple output terminals (first output terminal and second output terminal) that can simultaneously drive different gate lines. The output sub-circuit includes multiple output transistors (first output transistor and second output transistor) that can independently control different gate lines, enabling a single shift register to perform the function of multiple shift registers and thereby reducing the overall circuit area.
2Adaptability or versatility
If multiple shift registers are cascaded to scan multiple gate lines, then the scanning capability is improved, but the number of components increases and space is consumed
Solution Approach 1:
Multiple output functions are merged into a single shift register by integrating multiple output sub-circuits within one shift register unit. The first output sub-circuit and second output sub-circuit are combined in the same shift register, allowing simultaneous driving of multiple gate lines without requiring separate shift registers for each gate line.
3Area of stationary object
If the shift register structure is expanded to drive multiple gate lines, then the space efficiency is improved, but the circuit complexity within the shift register increases
Solution Approach 1:
The output driver circuit is segmented into multiple independent output sub-circuits, each with its own output transistor and control logic. This segmentation allows each sub-circuit to be designed and optimized independently while working together within the unified shift register structure, managing complexity through modular organization.
Data Source
AI summary
A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.