Shift Register Multi-Pulse Output for Pixel Sensing
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Solution Overview
Problem
Existing shift registers in display panels cannot achieve multiple pulse outputs during non-display stages, limiting the ability to detect pixel circuits and affecting display performance due to their simple output structure.
Innovation Solution
The shift register design includes an input sub-circuit, sensing control sub-circuit, output sub-circuit, first reset sub-circuit, and pull-down sub-circuit, which allows for multi-pulse output by controlling signal flow through various transistors and capacitors, enabling scanning signal output in both display and sensing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the shift register uses a simple output structure, then the device complexity is reduced, but the capability to output scanning signals in non-display stages is limited
Solution Approach 1:
The output structure is segmented into multiple independent sub-circuits (input sub-circuit, sensing control sub-circuit, output sub-circuit, first reset sub-circuit, and pull-down sub-circuit), each responsible for specific functions. This segmentation enables the shift register to output multiple scanning signals simultaneously in different stages while keeping each sub-circuit relatively simple and manageable.
Solution Approach 2:
The output structure is designed with multi-functionality to serve both display stages and non-display (sensing) stages. The sensing control sub-circuit and multiple output terminals enable the same shift register structure to perform different functions (display scanning and pixel sensing) without requiring separate dedicated circuits for each function.
2Measurement precision
If the shift register outputs multiple scanning signals in non-display stages, then the pixel circuit detection capability is improved, but the device complexity increases
Solution Approach 1:
The detection capability is enhanced by segmenting the output function into multiple independent output terminals and corresponding control sub-circuits. This allows simultaneous detection of multiple pixel circuits in non-display stages while maintaining clear functional separation, making the complex detection capability manageable through modular design.
Solution Approach 2:
The shift register is designed to output scanning signals in advance during non-display stages before the actual display operation. This preliminary action enables pixel circuit parameters to be detected and compensated beforehand, improving measurement precision without interfering with the subsequent display function.
3Adaptability or versatility
If the shift register structure is simplified, then the manufacturing process is easier, but the ability to provide scanning signals in both display and sensing stages is limited
Solution Approach 1:
The shift register employs a universal output structure that can operate in both display and sensing stages through the same basic circuit topology. The sensing control sub-circuit activates additional functionality during sensing stages while reusing the same transistor and capacitor components, avoiding the need for completely separate circuits and simplifying the manufacturing process.
Solution Approach 2:
The circuit operates dynamically by switching between different functional modes (display mode and sensing mode) based on control signals. The same physical structure adapts its behavior through dynamic control of transistor switching and signal routing, providing multi-stage scanning capability without requiring multiple static circuit configurations that would complicate manufacturing.
Data Source
AI summary
A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).