Shift Register Multi-Line Clocking for Lower Display Power
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Solution Overview
Problem
In display devices, driver circuits utilizing unipolar TFTs face issues with power consumption due to parasitic capacitance, particularly in inverted staggered TFTs, leading to increased power consumption of clock signals.
Innovation Solution
The implementation of a shift register with multiple pulse signal lines that supply clock signals during specific operation periods, reducing the capacity load and power consumption by distributing the clock signal supply across multiple wirings rather than a single wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal line is used to supply clock signals to all flip-flops, then the device complexity is reduced, but the power consumption increases due to large parasitic capacitance load
Solution Approach 1:
The patent divides a single clock signal line into multiple separate clock signal lines (first clock signal line, second clock signal line, third clock signal line, fourth clock signal line). Each line supplies clock signals to specific groups of flip-flops during different time periods, segmenting the overall clock distribution task to reduce the capacitive load on each individual line and thereby reducing power consumption.
Solution Approach 2:
The patent implements periodic clock signal supply where different clock signal lines are activated during different time periods. For example, the first clock signal line supplies clock signals during a first period, while the second clock signal line supplies clock signals during a second period that overlaps with the first period. This periodic distribution reduces the simultaneous capacitive load on any single line.
2Power
If the gate width of TFTs is increased to handle heavy driver circuit load, then the driving capability is improved, but the parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The patent segments the driver circuit into multiple flip-flops that are distributed across different clock signal lines. This segmentation allows the use of TFTs with smaller gate widths since each TFT only needs to drive a portion of the total load during its assigned time period, thereby reducing parasitic capacitance while maintaining sufficient driving capability.
Solution Approach 2:
By activating different clock signal lines during different time periods, the patent distributes the driving load temporally. This periodic action allows TFTs to handle smaller instantaneous loads, reducing the need for large gate widths and associated parasitic capacitance, while still maintaining the overall driving capability of the driver circuit.
Data Source
AI summary
The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.