Shift Register Layout for Narrow-Bezel Display Substrates
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Solution Overview
Problem
The existing design of gate drive circuits in display panels, particularly in flexible AMOLED displays, results in high parasitic capacitance and complex wiring, which hinders the achievement of a narrow frame design and affects display quality due to signal interference.
Innovation Solution
Optimized circuit connection and layout of the shift register unit on the display substrate, reducing overlapping wiring lines and complexity, thereby increasing space utilization and facilitating a narrow frame design while maintaining display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional gate drive circuit layout is used, then circuit functionality is achieved, but parasitic capacitance increases and wiring becomes complex
Solution Approach 1:
The gate drive circuit is divided into multiple independent shift register units, each handling a specific row or column of pixels. This segmentation allows for modular layout optimization, reducing the overall wiring complexity while maintaining signal integrity in each segment.
Solution Approach 2:
The circuit layout transitions from planar wiring to a three-dimensional stacked architecture, where signal lines are routed through multiple layers. This dimensional change allows signals to bypass overlapping connections, reducing parasitic capacitance while maintaining compact footprint.
2Ease of operation
If more wiring lines are used to achieve circuit functionality, then signal transmission is enabled, but space utilization decreases and frame width increases
Solution Approach 1:
Multiple signal lines are nested within each other by routing them through different vertical layers of the substrate. This nesting approach allows multiple signals to occupy the same horizontal space at different heights, reducing the overall frame width while maintaining full signal transmission capability.
Solution Approach 2:
The patent utilizes multi-layer substrate architecture to route signal lines in the vertical dimension. This allows signal transmission without increasing the horizontal footprint, thereby reducing frame width while maintaining ease of operation.
3Area of stationary object
If wiring lines overlap to save space, then space utilization increases, but parasitic capacitance increases and signal interference occurs
Solution Approach 1:
Signal lines that would otherwise overlap in the horizontal plane are separated by routing them through different vertical layers. This three-dimensional separation maintains high space utilization while eliminating parasitic capacitance and signal interference associated with planar overlaps.
Solution Approach 2:
Insulating layers and dielectric materials are introduced as intermediaries between closely spaced signal lines in different layers. These intermediaries prevent direct electromagnetic coupling, reducing parasitic capacitance and signal interference while allowing compact routing.
Data Source
Figure 1A
Figure 1B~1C
Figure 1D~2
AI summary
A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a base substrate (101), a shift register unit (104), a first clock signal line (GCK) and a second clock signal line (GCB). The shift register unit (104) comprises an input circuit (1041), an output circuit (1043), a first control circuit (1042), a second control circuit (1045), and a voltage stabilizing circuit (1046). A first electrode (SD71) of a first noise reduction transistor (T7) of the second control circuit (1045) of the shift register unit (104) and a first electrode (SD81) of a voltage stabilizing transistor (T8) of the voltage stabilizing circuit (1046) of the shift register unit (104) are located at a first source/drain electrode layer, the first source/drain electrode layer comprises a first bridge electrode (E1), the first bridge electrode (E1) comprises a first portion (E11) and a second portion (E12), the first portion (E11) is connected to the first electrode (SD71) of the first noise reduction transistor (T7) and the first electrode (SD81) of the voltage stabilizing transistor (T8), and the second portion (E12) is connected to a gate electrode (G2) of a first control transistor (T2) of the first control circuit (1042). The wiring of the shift register unit (104) is simpler, which is beneficial for increasing the space utilization rate of the display substrate, such that it is easier to achieve a narrow frame of the display substrate.