Shift Register Circuit for Narrow Bezel Display Panels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current display panel manufacturing techniques require multiple gate driver chips along the edges, increasing costs and limiting the competitiveness of display panels due to the need for a row-wise scan function, which complicates the design and increases production expenses.
Innovation Solution
A shift register design incorporating an input module, first and second reset modules, and an output module, connected in a specific configuration to eliminate the need for multiple gate driver chips by cascading shift registers and using clock and reset signals to control node connections, allowing for a narrow bezel and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple gate driver chips are arranged along the edges of the display panel to perform row-wise scan function, then the display panel can achieve proper signal distribution and control, but the manufacturing cost increases and the bezel width cannot be reduced
Solution Approach 1:
The patent merges multiple gate driver chip functions into a single integrated shift register circuit by cascading multiple shift register units (first shift register unit, second shift register unit, third shift register unit, fourth shift register unit) that can be fabricated on the same substrate as the display panel. This integration eliminates the need for separate gate driver chips, reducing manufacturing cost and enabling narrower bezels while maintaining the row-wise scan function.
Solution Approach 2:
The shift register circuit performs multiple functions: it generates clock signals, stores signal levels, controls switching of light-emitting elements, and enables bidirectional scanning (row-wise and column-wise). The same circuit structure can be configured for different scanning modes by changing the connection relationships between shift register units, providing universal functionality that replaces multiple specialized gate driver chips.
2Length of moving object
If gate driver chips are integrated at the edge of the display panel, then the bezel width can be reduced, but the manufacturing complexity and production cost increase
Solution Approach 1:
The gate driver function is segmented into multiple independent shift register units (first, second, third, and fourth shift register units), each capable of operating semi-independently. These units are cascaded together to form the complete gate driver circuit, allowing the circuit to be configured for different scanning modes (row-wise or column-wise) by selectively connecting the units, thereby reducing bezel width while managing complexity through modular design.
3Reliability
If a row-wise scan function is implemented using conventional gate driver chips, then proper signal control is achieved, but the production cost and device complexity increase
Solution Approach 1:
The shift register units generate their own clock signals and store signal levels internally using capacitors (first capacitor, second capacitor, third capacitor, fourth capacitor). Each unit can operate autonomously to a certain extent, with the cascade connection enabling coordinated operation across the entire display panel. This self-service capability maintains reliable signal control while eliminating the need for external gate driver chips, thereby reducing device complexity.
Data Source
AI summary
A shift register, a driving method therefor, a gate driving circuit and a display device. The shift register comprises: an input module, a first reset module, a second reset module, an output module. The input module is configured to write input signal of a signal input terminal STU into second node Q2 through second clock signal terminal CLKB, and to connect Q2 with first node Q1 through STU. The first reset module is configured to write signal of first direct current signal terminal into third node Q3 through STU, and to write reset signal of reset signal terminal STD into Q3 and connect Q2 with Q1 through STD. The second reset module is configured to write a signal of the first direct current signal terminal into a signal output terminal OUT through Q3. The output module is configured to write a first clock signal of CLKA into OUT through Q1.