Shift Register Design for Narrow Border Gate Driving Circuits
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Solution Overview
Problem
Conventional gate driving circuits require a large number of transistors and occupy a significant layout area, making it difficult to narrow the border of display panels due to the need for line-by-line scanning and the use of multiple inverters.
Innovation Solution
A shift register design that includes specific transistors and storage capacitors, triggered by a high-level signal, allowing direct cascading of shift registers between adjacent pixel rows without additional inverters, reducing the number of transistors and layout area in the gate driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional gate driving circuit uses line-by-line scanning with multiple inverters, then scanning function is achieved, but number of transistors increases and layout area expands
Solution Approach 1:
The patent extracts and eliminates the inverter portion from the conventional gate driving circuit. By removing the inverter stage and using a shift register triggered by high level directly, the circuit achieves the same scanning function with fewer transistors, thus resolving the contradiction between scanning functionality and device complexity
Solution Approach 2:
The patent inverts the traditional triggering mechanism from low level to high level. This inversion allows the shift register to be directly triggered without requiring subsequent inverter stages, reducing the transistor count while maintaining the line-by-line scanning function
2Ease of operation
If conventional gate driving circuit uses line-by-line scanning with multiple inverters, then scanning function is achieved, but layout area increases
Solution Approach 1:
The patent removes the inverter portion from the circuit architecture. By extracting this unnecessary component and using a direct high-level triggered shift register, the layout area is significantly reduced while preserving the scanning function, thus resolving the contradiction between functionality and area
Solution Approach 2:
The patent merges the shift register function with the triggering function by using a high-level triggered design. This integration eliminates the need for separate inverter stages, combining multiple functions into a single compact structure that reduces overall layout area
Data Source
AI summary
Embodiments of the disclosure provide a shift register, a driving method and a gate driving circuit. In an embodiment, the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor. The shift register is driven by the cooperation of the respective transistors. In the case that the shift register is applied in the gate driving circuit to implement a line-by-line scanning, shift registers corresponding to two adjacent pixel rows are cascaded directly and no inverters are provided following the shift registers corresponding to the respective pixel rows, thereby decreasing the number of transistors in the gate driving circuit, reducing the layout area of the gate driving circuit, and being advantageous for narrowing the border.