Shift Register Design for Narrow Pitch Displays
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Solution Overview
Problem
High-definition displays with transverse stripe pixel arrays face challenges in achieving narrow pixel pitch and framing due to increased circuit width and manufacturing process constraints, particularly in shift register design.
Innovation Solution
A shift register design featuring multiple output circuits controlled by phase-different clock signals and shared control signal lines, allowing for reduced transistor count and enabling narrow pitch and framing, with options for NMOS or PMOS transistors to minimize manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a shift register is designed to drive high-definition displays with transverse stripe pixel arrays, then the display resolution and information capacity are improved, but the circuit width increases and manufacturing complexity increases
Solution Approach 1:
The shift register is divided into multiple stages, with each stage capable of driving a specific number of gate bus lines. This segmentation allows the total driving capacity to be distributed across multiple simpler units, reducing the complexity of each individual circuit while maintaining high overall resolution capability
Solution Approach 2:
Each shift register stage is designed with multi-functionality to drive multiple gate bus lines (e.g., 2 or 3 lines per stage) through shared control signal lines. This universal design reduces the total number of transistors needed compared to dedicated one-to-one driving circuits, thereby reducing circuit width while maintaining high display resolution
2Measurement precision
If multiple output circuits are used to drive gate bus lines in transverse stripe systems, then the display resolution is improved, but the number of transistors and manufacturing cost increase
Solution Approach 1:
Multiple output circuits share common control signal lines and control transistors. Specifically, the control transistors for selecting which output circuit is active are shared across multiple output stages, reducing the total transistor count while maintaining the capability to drive multiple gate bus lines independently
Solution Approach 2:
The control signal lines are designed to serve multiple output circuits simultaneously. A single set of control signal lines can selectively enable different output circuits based on the required driving pattern, making the control structure universal and reducing the number of control transistors needed
3Ease of manufacture
If NMOS or PMOS transistors are used instead of CMOS, then manufacturing cost is reduced, but circuit functionality may be limited
Solution Approach 1:
The invention adjusts the circuit parameters and configuration to ensure proper operation with single-polarity transistors. By modifying the circuit topology and signal levels, the design achieves full functionality using only NMOS or only PMOS transistors, eliminating the need for complex CMOS processes while maintaining circuit versatility
Data Source
AI summary
A shift register comprises: a first output circuit controlled by a first clock signal to output a signal to a first output signal line; a second output circuit controlled by a second clock signal with a phase different from a phase of the first clock signal to output a signal to a second output signal line; a first control signal line connected to the first and second output circuits; and a second control signal line connected to the first and second output circuits.