Bidirectional Shift Register Without Inverters for Stable Low Power
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Solution Overview
Problem
Conventional bidirectional shift registers in display technologies suffer from high power consumption due to inverter structures and clock coupling effects, leading to unstable output waveforms.
Innovation Solution
A shift register design featuring a series connection of stages with specific transistor and capacitor configurations, utilizing MOS thin film transistors and eliminating inverter structures to reduce power consumption and stabilize output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If inverter structures are used in conventional bidirectional shift registers, then signal level conversion and buffering are achieved, but power consumption increases
Solution Approach 1:
The patent removes the inverter structure from the shift register circuit. Specifically, the capacitive load type inverter that was previously used for signal level conversion and buffering is completely eliminated. The circuit achieves its functionality through direct transistor switching and capacitor-based signal transmission without requiring the inverter intermediate stage, thereby reducing power consumption while maintaining the essential shift register operation.
Solution Approach 2:
The transistors in the patent perform multiple functions simultaneously. For example, the transistors are used for signal transmission, switching, and level conversion all in one configuration, eliminating the need for separate inverter structures. This multi-functional design reduces the overall device complexity and power consumption while maintaining the bidirectional shift register functionality.
2Reliability
If capacitive load type inverters are used for signal buffering, then signal levels are maintained, but clock coupling effects cause unstable output waveforms
Solution Approach 1:
The patent extracts and removes the capacitive load type inverter from the circuit. By eliminating this inverter structure, the source of clock coupling effects is removed, resulting in stable output waveforms. The circuit achieves signal buffering through alternative means that do not introduce the harmful clock coupling effects associated with the inverter structure.
Solution Approach 2:
The patent eliminates the inverter structure that caused clock coupling effects and unstable waveforms. By removing this problematic component, the circuit achieves both low power consumption and stable output waveforms simultaneously, converting the previously harmful inverter-induced effects into a beneficial simple and efficient circuit design.
3Adaptability or versatility
If conventional bidirectional shift register designs are used, then bidirectional signal shifting is achieved, but power consumption is high due to inverter structures
Solution Approach 1:
The patent removes the power-consuming inverter structures from the bidirectional shift register while preserving the bidirectional shifting capability. The forward and backward shift operations are achieved through direct transistor switching and capacitor-based signal transmission, eliminating the need for inverters in both forward and backward shift paths, thereby reducing power consumption.
Solution Approach 2:
The patent employs dynamic switching of transistors to achieve bidirectional signal shifting. The circuit can dynamically switch between forward and backward shift modes by controlling the switching states of the transistors, maintaining adaptability and versatility without relying on static inverter structures that consume power continuously.
Data Source
AI summary
A shift register comprising a plurality of shift register stages {SN}. Each shift register stage comprises a first input, a second input, a third input for receiving a first clock signal, a fourth input for receiving a second clock signal, an output for providing an output signal OUT(N), therefrom. The stages is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N−1)-th shift register stage SN−1 for receiving an output signal OUT(N−1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage SN+1 for providing the output signal OUT(N+1) thereto.