Shift Register Stage Layout Using Clock-Driven Node Discharge

The patent replaces the constant discharging voltage source with periodic clock pulses to discharge nodes. Instead of continuously supplying discharging voltage, the system uses periodically occurring clock signal edges (rising or falling edges) to trigger node discharge events. This periodic action reduces the continuous power load on the discharging voltage source line while maintaining reliable node discharge functionality through timing-synchronized discharge operations.

The patent enables nodes to discharge themselves using the existing clock signal edges without requiring a separate continuous discharging voltage source. The clock signal, which already exists in the circuit for timing purposes, is repurposed to provide the discharge trigger. This self-service approach eliminates the need for additional dedicated discharging power supply infrastructure, reducing the load on external discharging voltage source lines.

The patent makes the clock signal serve multiple functions: it provides timing control for the shift register operation and simultaneously serves as the discharge trigger for nodes. The same clock signal edges that coordinate data shifting also initiate node discharge events. This multi-functionality eliminates the need for separate control signals and reduces the number of switching devices required, thereby reducing the overall shift register size while maintaining full node control capability.

The patent merges the node discharge control function with the existing clock signal control mechanism. Instead of having separate control circuits for node discharge and shift operation, both functions are integrated into a single clock-synchronized control scheme. This merging reduces the number of independent control paths and switching devices needed in each stage, directly reducing the shift register area while preserving both node control and discharge functions.