Shift Register Circuit Node Potential Control
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Solution Overview
Problem
High voltages in shift register circuits cause threshold voltage drift and instability in gate scanning signals, leading to degraded performance in display devices.
Innovation Solution
A shift register circuit design that includes an input control circuit, an output control circuit, and a reset circuit, along with pull-down control circuits, to manage node potentials and supply clock and reference voltages, ensuring the first node potential is less than the active pulse signal potential, thereby reducing voltage drift and maintaining circuit stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate scan signal voltage is increased to fully turn on transistors, then the transistor switching performance is improved, but the threshold voltage drift and circuit instability worsen due to excessive voltage at internal nodes
Solution Approach 1:
The patent introduces a pull-down control circuit that dynamically adjusts the potential of internal nodes during different operation phases. During the reset phase, the pull-down circuit actively lowers the potential of the first node to a predetermined level (lower than the high level of the gate scan signal), preventing excessive voltage accumulation. This parameter control resolves the contradiction by maintaining transistor switching performance while preventing threshold voltage drift through controlled potential adjustment.
Solution Approach 2:
The patent employs a feedback mechanism where the output of the shift register circuit is fed back to the input through the pull-down control circuit. This feedback loop enables the circuit to monitor and adjust its own internal node potentials, ensuring that voltages remain within safe operating ranges. The feedback mechanism prevents instability by continuously correcting potential deviations that would otherwise lead to threshold voltage drift.
2Ease of operation
If the potential at internal nodes is increased to maintain operation, then the output control circuit operation is maintained, but the threshold voltage drift increases due to high voltage exposure
Solution Approach 1:
The patent segments the voltage control function into distinct circuits: the output control circuit maintains operation by providing necessary clock signals, while the pull-down control circuit separately manages the potential of internal nodes. This segmentation allows the output control circuit to operate effectively without being directly exposed to high voltages, as the pull-down circuit isolates and controls the internal node potentials independently.
Solution Approach 2:
The pull-down control circuit acts as an intermediary between the high-voltage output control circuit and the sensitive internal nodes. It mediates the voltage levels by introducing a reset signal that activates the pull-down transistors, thereby lowering internal node potentials to safe levels without disrupting the normal operation of the output control circuit. This intermediary function protects the internal nodes from excessive voltage while maintaining system operation.
3Productivity
If the gate scan signal operates at high voltage levels, then the display device performance is improved, but the shift register becomes unstable leading to degraded gate scanning signals
Solution Approach 1:
The patent implements periodic reset action through the pull-down control circuit. The reset signal is applied periodically to activate the pull-down transistors, which temporarily lower the potential of internal nodes during specific phases of the operation cycle. This periodic intervention prevents the accumulation of excessive voltage that would lead to instability, while allowing the gate scan signal to operate at high voltage levels during the active display refresh periods.
Data Source
AI summary
A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.