Shift Register Unit Node Stabilization for OLED Display Uniformity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current gate driving circuits for OLED displays face challenges in achieving high resolution and narrow bezel designs due to complex circuit structures, leading to issues such as poor display effects and uneven brightness caused by progressive sequential compensation methods.

Innovation Solution

A shift register unit with a specific configuration including a first input circuit, output circuit, control circuit, reset circuit, second input circuit, transmission circuit, and storage circuit is used to stabilize node levels, enabling random compensation and preventing multiple signal outputs, thus improving display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If progressive sequential compensation method is used, then gate driving circuit can be implemented, but display uniformity deteriorates due to uneven brightness and scanning lines

Engineering Contradiction:
Improvegate driving circuit functionalityVSAvoiddisplay uniformity
Core Design Contradiction:
ReliabilityVSIllumination intensity

Solution Approach 1:

The patent applies preliminary action by stabilizing node levels before signal output through dedicated storage circuits (first storage circuit connected to first node, second storage circuit connected to second node). These circuits prepare and maintain stable voltage levels in advance, preventing the uneven brightness and scanning line issues that occur with progressive sequential compensation methods.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If complex circuit structure is used to achieve high resolution, then display resolution improves, but device complexity increases leading to manufacturing difficulties

Engineering Contradiction:
Improvedisplay resolutionVSAvoidcircuit structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the gate driving circuit into distinct functional modules: first input circuit, output circuit, first control circuit, first reset circuit, second input circuit, second control circuit, and second reset circuit. Each module handles specific functions independently, which simplifies the overall design and manufacturing while achieving high resolution through the coordinated operation of these segmented components.

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple signal outputs occur, then signal transmission coverage increases, but display quality deteriorates due to signal interference

Engineering Contradiction:
Improvesignal transmission coverageVSAvoiddisplay quality
Core Design Contradiction:
ProductivityVSIllumination intensity

Solution Approach 1:

The patent implements feedback mechanisms through reset circuits that monitor and correct node levels. The first reset circuit resets the first node based on feedback from the second node level, and the second reset circuit resets the second node based on feedback from the first node level. This feedback control prevents multiple unintended signal outputs while maintaining proper signal transmission coverage.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3929905B1Shift register unit, gate drive circuit, display apparatus and drive method
Publication Date: 2024.08.14 BOE TECHNOLOGY GROUP CO LTD
  • EP3929905B1 patent drawingFigure 1
  • EP3929905B1 patent drawingFigure 2
  • EP3929905B1 patent drawingFigure 3

AI summary

Provided are a shift register unit (10), a gate drive circuit (20), a display apparatus (1) and a drive method. A level of a second node (QB) can be better stabilized. The shift register unit (10) comprises a first input circuit (110), an output circuit (120), a first control circuit (130), a first reset circuit (140), a second input circuit (150), a transmission circuit (160) and a storage circuit (170), wherein the first input circuit (110) is configured to control a level of a first node (Q) in response to a first input signal (STU1); the output circuit (120) is configured to provide an output signal at an output end (OP) under the control of the level of the first node (Q); the first control circuit (130) is configured to control a level of a second node (QB) under the control of the level of the first node (Q); the first reset circuit (140) is configured to reset the first node (Q) and the output end (OP) under the control of the level of the second node (QB); and the storage circuit (170) is electrically connected to the second node (QB) and is configured to stabilize the level of the second node (QB).