Shift Register Node Control Transistor Noise Immunity
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Solution Overview
Problem
Shift registers in display devices are prone to malfunction due to noise interference on low-level potential VSS, particularly in multi-stage configurations, leading to charge escape and operational failures.
Innovation Solution
A shift register configuration with a node control unit that includes control transistors to manage node potentials, ensuring they remain off-level even when noise affects the power supply, using control signals to prevent charge escape and maintain stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-stage shift register configuration is used, then the display device can selectively scan pixel circuits in unit of row, but noise interference on the low-level potential VSS causes malfunction and charge escape
Solution Approach 1:
The patent introduces a node control unit as an intermediary component between the power supply and the unit circuits. This unit control transistors that actively manage the potential of internal nodes, preventing noise on VSS from directly affecting the floating nodes. The control unit acts as a buffer that isolates the sensitive internal nodes from power supply noise while maintaining proper potential levels.
Solution Approach 2:
The patent dynamically changes the potential parameters of internal nodes through controlled transistor switching. By adjusting the potential of floating nodes to match the off-level potential (VSS) during non-floating periods, the patent prevents noise-induced potential deviations. This parameter control ensures that even when VSS contains noise, the internal nodes maintain stable reference levels.
2Device complexity
If nodes are left in floating state, then the circuit operates efficiently with fewer active transistors, but noise on VSS causes charge escape and potential instability
Solution Approach 1:
The patent applies preliminary action by proactively controlling node potentials before noise can cause charge escape. The node control unit preemptively sets floating nodes to the off-level potential (VSS) during periods when they should not be floating, preventing noise-induced charge escape before it occurs. This preventive approach maintains reliability without requiring continuous active transistor operation.
3Reliability
If control transistors are added to manage node potentials, then noise resistance improves, but device complexity increases
Solution Approach 1:
The patent segments the shift register into multiple unit circuits, each with its own node control unit. This segmentation allows the noise resistance function to be distributed across multiple independent control transistors rather than requiring a single complex control mechanism. Each unit circuit manages its own floating nodes locally, reducing the overall system complexity while maintaining robust noise resistance.
Data Source
AI summary
A unit circuit 11 of a shift register is provided with a transistor Tr10 for supplying an off potential to a node n1 via a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr10. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr10. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Tr10 does not turn on and charge does not escape from the node 1. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.