Shift Register Output Stability via Node Voltage Control

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Solution Overview

Problem

Existing shift registers in liquid crystal display and OLED devices experience unstable outputs due to parasitic capacitance and pulse interference from clock signals, affecting the control of gate lines.

Innovation Solution

A shift register design comprising multiple control and output modules with transistors and capacitors, where node voltages are controlled to output stable ON or OFF voltages independently of clock signals, preventing interference and ensuring stable voltage outputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the transistor gate is directly controlled by clock signal pulses, then the shift register can be controlled to output signals, but the parasitic capacitance of the transistor causes unstable outputs

Engineering Contradiction:

Improvesignal output controlVSAvoidoutput stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces control nodes and capacitors as intermediary elements between the clock signal and the transistor gates. These intermediaries filter out the harmful pulse effects while preserving the useful control function, thereby stabilizing the output without sacrificing productivity

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful parasitic capacitance effect into a beneficial filtering mechanism. By intentionally adding capacitors at control nodes, the design uses capacitance to block high-frequency pulse noise while allowing the necessary control signals to pass through, thus transforming the problem into a solution

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS9761175B2Shift register and driving method thereof as well as gate driving circuit

Publication Date: 2017.09.12 BOE TECHNOLOGY GROUP CO LTD

AI summary

A shift register is proposed, comprising: a first control module connected to an ON voltage access terminal and a first node, for controlling whether to output an ON voltage and a first control signal to the first node; a second control module connected to the ON voltage access terminal, a second node and an output terminal, for controlling whether to output the ON voltage and a voltage of the output terminal to the second node; an output module connected to the first node, the second node, the output terminal, an OFF voltage access terminal, and the ON voltage access terminal, for inputting the ON or OFF voltage to the output terminal according to voltages of the first and second nodes; and an input module connected to an input terminal, for controlling whether to input a signal of the input terminal to the first and second control modules.