Shift Register Noise Reduction for LCD GOA Circuits

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Solution Overview

Problem

In liquid crystal displays (LCDs), the GOA circuit's shift register experiences noise interference and reduced stability during blanking time due to incomplete charge release from internal nodes and transistors, affecting display quality.

Innovation Solution

A shift register design incorporating a pull-up control circuit, pull-down control circuit, reset circuit, and noise reduction control circuit, along with an auxiliary noise reduction module, to manage node voltages and prevent signal output during blanking time, ensuring complete charge release and reducing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the GOA circuit operates during blanking time to complete scanning, then scanning continuity is improved, but noise interference increases due to incomplete charge release

Engineering Contradiction:
Improvescanning continuityVSAvoidnoise interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by activating the noise reduction control circuit before the blanking period begins. This circuit proactively discharges residual charges from internal nodes through dedicated discharge paths (transistors M7-M10), preventing noise accumulation before it can interfere with the output signal during the blanking time when the shift register is inactive.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the noise reduction function as a separate control circuit independent from the main shift register operation. This dedicated noise reduction control circuit (with transistors M7-M10 and control signal STV_in) is specifically designed to remove harmful residual charges from internal nodes, separating the noise management function from the primary scanning function to eliminate interference without affecting scanning continuity.

Inventive Principle:
Principle #2Taking out (Extraction)

2Speed

If the shift register maintains signal output capability, then response speed is improved, but stability deteriorates due to residual charges from coupling capacitors

Engineering Contradiction:
Improveresponse speedVSAvoidcircuit stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces an intermediary noise reduction control circuit that mediates between the shift register's signal output function and the stability requirement. This control circuit acts as a mediator by selectively activating discharge paths during blanking time, allowing the shift register to maintain full signal output capability during active scanning while ensuring stability during inactive periods through controlled charge dissipation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies dynamics by making the discharge path activation dynamic rather than static. The noise reduction control circuit responds to the blanking control signal STV_in, dynamically enabling discharge paths only when needed during blanking time. This dynamic approach allows the circuit to maintain high response speed during active operation while automatically stabilizing during blanking periods, adapting its behavior to operational requirements.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10950196B2Shift register, method for driving the same, gate driving circuit, and display device
Publication Date: 2021.03.16 BOE TECHNOLOGY GROUP CO LTD
  • US10950196B2 patent drawing
  • US10950196B2 patent drawing
  • US10950196B2 patent drawing

AI summary

A shift register, a method for driving the same, a gate driving circuit, and a display device are described. The shift register includes a pull-up control circuit which outputs the voltage of a signal input terminal, a pull-up circuit which outputs the voltage of a first clock signal input terminal, a pull-down control circuit which outputs the voltage of a second clock signal input terminal, or pulls down the voltage of the pull-down node, a pull-down circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, a reset circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, and a noise reduction control circuit which outputs the voltage of a noise reduction control signal terminal to the pull-down node in the blanking time of an image frame.